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path: root/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
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* [Hexagon] Legalize vector elements to i32 in buildVector32/64Krzysztof Parzyszek2017-12-201-15/+22
| | | | llvm-svn: 321218
* [Hexagon] Adjust the value type for BCvt in LowerFormalArgumentsKrzysztof Parzyszek2017-12-201-2/+8
| | | | llvm-svn: 321177
* i[Hexagon] ANY_EXTEND_VECTOR_INREG should be Custom, not Legal in r321004Krzysztof Parzyszek2017-12-181-1/+2
| | | | llvm-svn: 321005
* [Hexagon] Generate HVX code for vector sign-, zero- and any-extendsKrzysztof Parzyszek2017-12-181-0/+5
| | | | | | Implement any-extend as zero-extend. llvm-svn: 321004
* [Hexagon] Prefer to widen HVX vectors instead of promotingKrzysztof Parzyszek2017-12-181-0/+12
| | | | llvm-svn: 321002
* MachineFunction: Return reference from getFunction(); NFCMatthias Braun2017-12-151-4/+4
| | | | | | The Function can never be nullptr so we can return a reference. llvm-svn: 320884
* TLI: Allow using PSV for intrinsic mem operandsMatt Arsenault2017-12-141-0/+1
| | | | llvm-svn: 320756
* DAG: Expose all MMO flags in getTgtMemIntrinsicMatt Arsenault2017-12-141-3/+3
| | | | | | | | | | | | | | Rather than adding more bits to express every MMO flag you could want, just directly use the MMO flags. Also fixes using a bunch of bool arguments to getMemIntrinsicNode. On AMDGPU, buffer and image intrinsics should always have MODereferencable set, but currently there is no way to do that directly during the initial intrinsic lowering. llvm-svn: 320746
* [Hexagon] Generate HVX code for comparisons and selectsKrzysztof Parzyszek2017-12-141-3/+14
| | | | llvm-svn: 320744
* [Hexagon] Remove vectors of i64 from valid HVX typesKrzysztof Parzyszek2017-12-141-39/+20
| | | | | | HVX does not support operations on 64-bit integers. llvm-svn: 320722
* [Hexagon] Add support for Hexagon V65Krzysztof Parzyszek2017-12-111-0/+38
| | | | llvm-svn: 320404
* [Hexagon] Generate HVX code for basic arithmetic operationsKrzysztof Parzyszek2017-12-071-2/+14
| | | | | | Handle and, or, xor, add, sub, mul for vectors of i8, i16, and i32. llvm-svn: 320063
* [Hexagon] Generate HVX code for vector construction and accessKrzysztof Parzyszek2017-12-061-215/+98
| | | | | | | | | | Support for: - build vector, - extract vector element, subvector, - insert vector element, subvector, - shuffle. llvm-svn: 319901
* [Hexagon] Remove HexagonISD::PACKHLKrzysztof Parzyszek2017-11-291-1/+0
| | | | llvm-svn: 319352
* [Hexagon] Create helpers extractVector and insertVector in loweringKrzysztof Parzyszek2017-11-291-135/+123
| | | | llvm-svn: 319351
* [Hexagon] Make sure to zero-extend bytes before building a vectorKrzysztof Parzyszek2017-11-281-10/+12
| | | | llvm-svn: 319204
* [Hexagon] Implement HexagonSubtarget::isHVXVectorTypeKrzysztof Parzyszek2017-11-271-27/+4
| | | | llvm-svn: 319064
* [Hexagon] Implement buildVector32 and buildVector64 as utility functionsKrzysztof Parzyszek2017-11-221-133/+141
| | | | | | | | | Change LowerBUILD_VECTOR to use those functions. This commit will tempora- rily affect constant vector generation (it will generate constant-extended values instead of non-extended combines), but the code for the general case should be better. The constant selection part will be fixed later. llvm-svn: 318877
* [Hexagon] Remove trailing spaces, NFCKrzysztof Parzyszek2017-11-221-1/+1
| | | | llvm-svn: 318875
* Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie2017-11-171-1/+1
| | | | | | | | All these headers already depend on CodeGen headers so moving them into CodeGen fixes the layering (since CodeGen depends on Target, not the other way around). llvm-svn: 318490
* [Hexagon] Return the correct chain edge for i1 function callsKrzysztof Parzyszek2017-10-231-1/+2
| | | | | | | | | | | | | | | | | In HexagonISelLowering, there is code to handle the case when a function returns an i1 type. In this case, we need to generate extra nodes to copy the result from R0 to a predicate register. The code was returning the wrong value for the chain edge which caused an assert "Wrong topological sorting" when converting the instructions to MIs. This patch fixes the problem by returning the chain for the final copy. Patch by Brendon Cahoon. llvm-svn: 316367
* [Hexagon] Report error instead of crashing on wrong inline-asm constraintsKrzysztof Parzyszek2017-10-201-13/+14
| | | | llvm-svn: 316236
* [Hexagon] Reorganize and update instruction patternsKrzysztof Parzyszek2017-10-201-0/+9
| | | | llvm-svn: 316228
* [Hexagon] New HVX target features.Sumanth Gundapaneni2017-10-181-33/+33
| | | | | | | | | | | | | | | | | | | | | | This patch lets the llvm tools handle the new HVX target features that are added by frontend (clang). The target-features are of the form "hvx-length64b" for 64 Byte HVX mode, "hvx-length128b" for 128 Byte mode HVX. "hvx-double" is an alias to "hvx-length128b" and is soon will be deprecated. The hvx version target feature is upgated form "+hvx" to "+hvxv{version_number}. Eg: "+hvxv62" For the correct HVX code generation, the user must use the following target features. For 64B mode: "+hvxv62" "+hvx-length64b" For 128B mode: "+hvxv62" "+hvx-length128b" Clang picks a default length if none is specified. If for some reason, no hvx-length is specified to llvm, the compilation will bail out. There is a corresponding clang patch. Differential Revision: https://reviews.llvm.org/D38851 llvm-svn: 316101
* [Hexagon] Update Hexagon ArchEnum and sync some downstream changes(NFC)Sumanth Gundapaneni2017-10-181-38/+24
| | | | | | Differential Revision: https://reviews.llvm.org/D38850 llvm-svn: 316099
* Remove unused variables. No functionality change.Benjamin Kramer2017-10-081-1/+0
| | | | llvm-svn: 315185
* [Hexagon] Patch to Extract i1 element from vector of i1Ron Lieberman2017-10-021-1/+7
| | | | | | | This patch extracts 1 element from vector consisting of elements of size 1 bit at given index. llvm-svn: 314641
* [Hexagon] Switch to parameterized register classes for HVXKrzysztof Parzyszek2017-09-151-34/+33
| | | | | | | This removes the duplicate HVX instruction set for the 128-byte mode. Single instruction set now works for both modes (64- and 128-byte). llvm-svn: 313362
* [Hexagon] Convert HVX vector constants of i1 to i8Krzysztof Parzyszek2017-08-011-0/+36
| | | | | | | | | Certain operations require vector of i1 values. However, for Hexagon architecture compatibility, they need to be represented as vector of i8. Patch by Suyog Sarda. llvm-svn: 309677
* TargetLowering: Change isShuffleMaskLegal's mask argument type to ↵Zvi Rackover2017-07-261-2/+2
| | | | | | | | | | | | | ArrayRef<int>. NFCI. Changing mask argument type from const SmallVectorImpl<int>& to ArrayRef<int>. This came up in D35700 where a mask is received as an ArrayRef<int> and we want to pass it to TargetLowering::isShuffleMaskLegal(). Also saves a few lines of code. llvm-svn: 309085
* [Hexagon] Add inline-asm constraint 'a' for modifier register classKrzysztof Parzyszek2017-07-211-2/+10
| | | | | | | For example asm ("memw(%0++%1) = %2" : : "r"(addr),"a"(mod),"r"(val) : "memory") llvm-svn: 308761
* [SystemZ, LoopStrengthReduce]Jonas Paulsson2017-07-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch makes LSR generate better code for SystemZ in the cases of memory intrinsics, Load->Store pairs or comparison of immediate with memory. In order to achieve this, the following common code changes were made: * New TTI hook: LSRWithInstrQueries(), which defaults to false. Controls if LSR should do instruction-based addressing evaluations by calling isLegalAddressingMode() with the Instruction pointers. * In LoopStrengthReduce: handle address operands of memset, memmove and memcpy as address uses, and call isFoldableMemAccessOffset() for any LSRUse::Address, not just loads or stores. SystemZ changes: * isLSRCostLess() implemented with Insns first, and without ImmCost. * New function supportedAddressingMode() that is a helper for TTI methods looking at Instructions passed via pointers. Review: Ulrich Weigand, Quentin Colombet https://reviews.llvm.org/D35262 https://reviews.llvm.org/D35049 llvm-svn: 308729
* [Hexagon] Remove custom lowering of loads of v4i16Krzysztof Parzyszek2017-07-171-82/+1
| | | | | | | The target-independent lowering works fine, except concatenating 32-bit words. Add a pattern to generate A2_combinew instead of 64-bit asl/or. llvm-svn: 308186
* [Hexagon] Replace ISD opcode VPACK with VPACKE/VPACKO, NFCKrzysztof Parzyszek2017-07-141-11/+9
| | | | | | This breaks up pack-even and pack-odd into two separate operations. llvm-svn: 308049
* [Hexagon] Use VSPLAT instead of COMBINE for vectors of type v2i32, NFCKrzysztof Parzyszek2017-07-131-23/+21
| | | | | | This cleans up the vector shift patterns. llvm-svn: 307935
* [Hexagon] Do not rely on callee-saved info in hasFPKrzysztof Parzyszek2017-07-111-2/+7
| | | | llvm-svn: 307675
* [Hexagon] Convert typed ISD opcodes to generic ones, NFCKrzysztof Parzyszek2017-07-101-19/+13
| | | | llvm-svn: 307582
* [Hexagon] Remove unused ISD opcodes, NFCKrzysztof Parzyszek2017-07-101-15/+0
| | | | llvm-svn: 307580
* [Hexagon] Implement frame pointer elimination with -fomit-frame-pointerKrzysztof Parzyszek2017-06-301-41/+36
| | | | | | | It applies to leaf functions that are otherwise not required to have a frame pointer. llvm-svn: 306888
* Sort the remaining #include lines in include/... and lib/....Chandler Carruth2017-06-061-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | I did this a long time ago with a janky python script, but now clang-format has built-in support for this. I fed clang-format every line with a #include and let it re-sort things according to the precise LLVM rules for include ordering baked into clang-format these days. I've reverted a number of files where the results of sorting includes isn't healthy. Either places where we have legacy code relying on particular include ordering (where possible, I'll fix these separately) or where we have particular formatting around #include lines that I didn't want to disturb in this patch. This patch is *entirely* mechanical. If you get merge conflicts or anything, just ignore the changes in this patch and run clang-format over your #include lines in the files. Sorry for any noise here, but it is important to keep these things stable. I was seeing an increasing number of patches with irrelevant re-ordering of #include lines because clang-format was used. This patch at least isolates that churn, makes it easy to skip when resolving conflicts, and gets us to a clean baseline (again). llvm-svn: 304787
* [Hexagon] Improve code generation for 32x32-bit multiplicationKrzysztof Parzyszek2017-05-301-5/+1
| | | | | | | | | For multiplications of 64-bit values (giving 64-bit result), detect cases where the arguments are sign-extended 32-bit values, on a per- operand basis. This will allow few patterns to match a wider variety of combinations in which extensions can occur. llvm-svn: 304223
* [SelectionDAG] Set ISD::FPOWI to Expand by defaultCraig Topper2017-05-301-1/+1
| | | | | | | | | | | | | | | | | Summary: Currently FPOWI defaults to Legal and LegalizeDAG.cpp turns Legal into Expand for this opcode because Legal is a "lie". This patch changes the default for this opcode to Expand and removes the hack from LegalizeDAG.cpp. It also removes all the code in the targets that set this opcode to Expand themselves since they can just rely on the default. Reviewers: spatel, RKSimon, efriedma Reviewed By: RKSimon Subscribers: jfb, dschuff, sbc100, jgravelle-google, nemanjai, javed.absar, andrew.w.kaylor, llvm-commits Differential Revision: https://reviews.llvm.org/D33530 llvm-svn: 304215
* Add extra operand to CALLSEQ_START to keep frame part set up previouslySerge Pavlov2017-05-091-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using arguments with attribute inalloca creates problems for verification of machine representation. This attribute instructs the backend that the argument is prepared in stack prior to CALLSEQ_START..CALLSEQ_END sequence (see http://llvm.org/docs/InAlloca.htm for details). Frame size stored in CALLSEQ_START in this case does not count the size of this argument. However CALLSEQ_END still keeps total frame size, as caller can be responsible for cleanup of entire frame. So CALLSEQ_START and CALLSEQ_END keep different frame size and the difference is treated by MachineVerifier as stack error. Currently there is no way to distinguish this case from actual errors. This patch adds additional argument to CALLSEQ_START and its target-specific counterparts to keep size of stack that is set up prior to the call frame sequence. This argument allows MachineVerifier to calculate actual frame size associated with frame setup instruction and correctly process the case of inalloca arguments. The changes made by the patch are: - Frame setup instructions get the second mandatory argument. It affects all targets that use frame pseudo instructions and touched many files although the changes are uniform. - Access to frame properties are implemented using special instructions rather than calls getOperand(N).getImm(). For X86 and ARM such replacement was made previously. - Changes that reflect appearance of additional argument of frame setup instruction. These involve proper instruction initialization and methods that access instruction arguments. - MachineVerifier retrieves frame size using method, which reports sum of frame parts initialized inside frame instruction pair and outside it. The patch implements approach proposed by Quentin Colombet in https://bugs.llvm.org/show_bug.cgi?id=27481#c1. It fixes 9 tests failed with machine verifier enabled and listed in PR27481. Differential Revision: https://reviews.llvm.org/D32394 llvm-svn: 302527
* [Hexagon] Add extenders for GD_PLT_B22_PCREL and LD_PLT_B22_PCRELKrzysztof Parzyszek2017-05-021-1/+6
| | | | | | Patch by Sid Manning. llvm-svn: 301955
* DAG: Make mayBeEmittedAsTailCall parameter constMatt Arsenault2017-04-181-1/+1
| | | | llvm-svn: 300603
* [Hexagon] Implement HexagonTargetLowering::CanLowerReturnKrzysztof Parzyszek2017-04-131-12/+13
| | | | | | | | Patch by Michael Wu. Differential Revision: https://reviews.llvm.org/D32000 llvm-svn: 300199
* [Hexagon] Fix "LowerFormalArguments emitted a value with the wrong type!" ↵Krzysztof Parzyszek2017-04-131-1/+1
| | | | | | | | | | assertion Patch by Michael Wu. Differential Revision: https://reviews.llvm.org/D31999 llvm-svn: 300198
* [Hexagon] Properly handle 'q' constraint in 128-byte vector modeKrzysztof Parzyszek2017-03-021-22/+10
| | | | llvm-svn: 296772
* [Hexagon] Fix lowering of formal arguments of type i1Krzysztof Parzyszek2017-03-011-3/+20
| | | | | | | | | | | On Hexagon, values of type i1 are passed in registers of type i32, even though i1 is not a legal value for these registers. This is a special case and needs special handling to maintain consistency of the lowering information. This fixes PR32089. llvm-svn: 296645
* [Hexagon] Patterns for CTPOP, BSWAP and BITREVERSEKrzysztof Parzyszek2017-02-231-15/+7
| | | | llvm-svn: 295981
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