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| author | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2017-11-28 19:13:17 +0000 |
|---|---|---|
| committer | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2017-11-28 19:13:17 +0000 |
| commit | 081e458e90ef6853aabf8c93028538cecdc31a8a (patch) | |
| tree | 63b75a7a1c3724a305f2f75e5f4807ed1c9979f3 /llvm/lib/Target/Hexagon/HexagonISelLowering.cpp | |
| parent | b1a97d37742b8b15e375b10777c1f05af3d410a1 (diff) | |
| download | bcm5719-llvm-081e458e90ef6853aabf8c93028538cecdc31a8a.tar.gz bcm5719-llvm-081e458e90ef6853aabf8c93028538cecdc31a8a.zip | |
[Hexagon] Make sure to zero-extend bytes before building a vector
llvm-svn: 319204
Diffstat (limited to 'llvm/lib/Target/Hexagon/HexagonISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonISelLowering.cpp | 22 |
1 files changed, 12 insertions, 10 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp index 3ecc2867907..2005ca6360c 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -2499,16 +2499,18 @@ HexagonTargetLowering::buildVector32(ArrayRef<SDValue> Elem, const SDLoc &dl, // (zxtb(Elem[0]) | (zxtb(Elem[1]) << 8)) | // (zxtb(Elem[2]) | (zxtb(Elem[3]) << 8)) << 16 SDValue S8 = DAG.getConstant(8, dl, MVT::i32); - SDValue S16 = DAG.getConstant(16, dl, MVT::i32); - SDValue V0 = DAG.getZExtOrTrunc(Elem[0], dl, MVT::i32); - SDValue V1 = DAG.getZExtOrTrunc(Elem[2], dl, MVT::i32); - SDValue V2 = DAG.getNode(ISD::SHL, dl, MVT::i32, {Elem[1], S8}); - SDValue V3 = DAG.getNode(ISD::SHL, dl, MVT::i32, {Elem[3], S8}); - SDValue V4 = DAG.getNode(ISD::OR, dl, MVT::i32, {V0, V2}); - SDValue V5 = DAG.getNode(ISD::OR, dl, MVT::i32, {V1, V3}); - SDValue V6 = DAG.getNode(ISD::SHL, dl, MVT::i32, {V5, S16}); - SDValue V7 = DAG.getNode(ISD::OR, dl, MVT::i32, {V4, V6}); - return DAG.getBitcast(MVT::v4i8, V7); + SDValue V0 = DAG.getZeroExtendInReg(Elem[0], dl, MVT::i8); + SDValue V1 = DAG.getZeroExtendInReg(Elem[1], dl, MVT::i8); + SDValue V2 = DAG.getZeroExtendInReg(Elem[2], dl, MVT::i8); + SDValue V3 = DAG.getZeroExtendInReg(Elem[3], dl, MVT::i8); + + SDValue V4 = DAG.getNode(ISD::SHL, dl, MVT::i32, {V1, S8}); + SDValue V5 = DAG.getNode(ISD::SHL, dl, MVT::i32, {V3, S8}); + SDValue V6 = DAG.getNode(ISD::OR, dl, MVT::i32, {V0, V4}); + SDValue V7 = DAG.getNode(ISD::OR, dl, MVT::i32, {V2, V5}); + SDNode *T0 = DAG.getMachineNode(Hexagon::A2_combine_ll, dl, MVT::i32, + {V7, V6}); + return DAG.getBitcast(MVT::v4i8, SDValue(T0,0)); } SDValue |

