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* [SelectionDAG] Disallow indirect "i" constraintFangrui Song2019-12-291-1/+0
| | | | | | | | | This allows us to delete InlineAsm::Constraint_i workarounds in SelectionDAGISel::SelectInlineAsmMemoryOperand overrides and TargetLowering::getInlineAsmMemConstraint overrides. They were introduced to X86 in r237517 to prevent crashes for constraints like "=*imr". They were later copied to other targets.
* [IR] Split out target specific intrinsic enums into separate headersReid Kleckner2019-12-111-1/+2
| | | | | | | | | | | | | | | | | | | | This has two main effects: - Optimizes debug info size by saving 221.86 MB of obj file size in a Windows optimized+debug build of 'all'. This is 3.03% of 7,332.7MB of object file size. - Incremental step towards decoupling target intrinsics. The enums are still compact, so adding and removing a single target-specific intrinsic will trigger a rebuild of all of LLVM. Assigning distinct target id spaces is potential future work. Part of PR34259 Reviewers: efriedma, echristo, MaskRay Reviewed By: echristo, MaskRay Differential Revision: https://reviews.llvm.org/D71320
* [Hexagon] Update PS_aligna with max stack alignment once isel completesKrzysztof Parzyszek2019-11-121-3/+14
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* [Hexagon] Don't dereference dyn_cast<ConstantFPSDNode> result. NFCI.Simon Pilgrim2019-09-221-1/+1
| | | | | | The static analyzer is warning about potential null dereference, but we should be able to use cast<ConstantFPSDNode> directly and if not assert will fire for us. llvm-svn: 372499
* [Hexagon] Split vector pairs for ISD::SIGN_EXTEND and ISD::ZERO_EXTENDKrzysztof Parzyszek2019-02-201-0/+5
| | | | llvm-svn: 354473
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
| | | | | | | | | | | | | | | | | to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
* Fix clang -Wimplicit-fallthrough warnings across llvm, NFCReid Kleckner2018-11-011-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch should not introduce any behavior changes. It consists of mostly one of two changes: 1. Replacing fall through comments with the LLVM_FALLTHROUGH macro 2. Inserting 'break' before falling through into a case block consisting of only 'break'. We were already using this warning with GCC, but its warning behaves slightly differently. In this patch, the following differences are relevant: 1. GCC recognizes comments that say "fall through" as annotations, clang doesn't 2. GCC doesn't warn on "case N: foo(); default: break;", clang does 3. GCC doesn't warn when the case contains a switch, but falls through the outer case. I will enable the warning separately in a follow-up patch so that it can be cleanly reverted if necessary. Reviewers: alexfh, rsmith, lattner, rtrieu, EricWF, bollu Differential Revision: https://reviews.llvm.org/D53950 llvm-svn: 345882
* [SDAG] Remove the reliance on MI's allocation strategy forChandler Carruth2018-08-141-11/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | `MachineMemOperand` pointers attached to `MachineSDNodes` and instead have the `SelectionDAG` fully manage the memory for this array. Prior to this change, the memory management was deeply confusing here -- The way the MI was built relied on the `SelectionDAG` allocating memory for these arrays of pointers using the `MachineFunction`'s allocator so that the raw pointer to the array could be blindly copied into an eventual `MachineInstr`. This creates a hard coupling between how `MachineInstr`s allocate their array of `MachineMemOperand` pointers and how the `MachineSDNode` does. This change is motivated in large part by a change I am making to how `MachineFunction` allocates these pointers, but it seems like a layering improvement as well. This would run the risk of increasing allocations overall, but I've implemented an optimization that should avoid that by storing a single `MachineMemOperand` pointer directly instead of allocating anything. This is expected to be a net win because the vast majority of uses of these only need a single pointer. As a side-effect, this makes the API for updating a `MachineSDNode` and a `MachineInstr` reasonably different which seems nice to avoid unexpected coupling of these two layers. We can map between them, but we shouldn't be *surprised* at where that occurs. =] Differential Revision: https://reviews.llvm.org/D50680 llvm-svn: 339740
* [SelectionDAG] Expand UADDO/USUBO into ADD/SUBCARRY if legal for targetKrzysztof Parzyszek2018-06-011-0/+12
| | | | | | | | | Additionally, implement handling of ADD/SUBCARRY on Hexagon, utilizing the UADDO/USUBO expansion. Differential Revision: https://reviews.llvm.org/D47559 llvm-svn: 333751
* [Hexagon] Generate post-increment for floating point typesBrendon Cahoon2018-05-181-0/+4
| | | | | | | | | | The code that generates post-increments for Hexagon considered integer values only. This patch adds support to generate them for floating point values, f32 and f64. Differential Revision: https://reviews.llvm.org/D47036 llvm-svn: 332748
* Rename DEBUG macro to LLVM_DEBUG.Nicola Zaghen2018-05-141-25/+25
| | | | | | | | | | | | | | | | The DEBUG() macro is very generic so it might clash with other projects. The renaming was done as follows: - git grep -l 'DEBUG' | xargs sed -i 's/\bDEBUG\s\?(/LLVM_DEBUG(/g' - git diff -U0 master | ../clang/tools/clang-format/clang-format-diff.py -i -p1 -style LLVM - Manual change to APInt - Manually chage DOCS as regex doesn't match it. In the transition period the DEBUG() macro is still present and aliased to the LLVM_DEBUG() one. Differential Revision: https://reviews.llvm.org/D43624 llvm-svn: 332240
* Remove \brief commands from doxygen comments.Adrian Prantl2018-05-011-1/+1
| | | | | | | | | | | | | | | | We've been running doxygen with the autobrief option for a couple of years now. This makes the \brief markers into our comments redundant. Since they are a visual distraction and we don't want to encourage more \brief markers in new code either, this patch removes them all. Patch produced by for i in $(git grep -l '\\brief'); do perl -pi -e 's/\\brief //g' $i & done Differential Revision: https://reviews.llvm.org/D46290 llvm-svn: 331272
* [Hexagon] Improve HVX instruction selection (bitcast, vsplat)Krzysztof Parzyszek2018-04-201-17/+0
| | | | | | | | | | There was some unfortunate interaction between VSPLAT and BITCAST related to the selection of constant vectors (coming from selecting shuffles). Introduce VSPLATW that always splats a 32-bit word, and can have arbitrary result type (to avoid BITCASTs of VSPLAT). Clean up the previous selection of BITCAST/VSPLAT. llvm-svn: 330471
* [Hexagon] Pass pointer to SelectionDAG to dump functionsKrzysztof Parzyszek2018-03-301-5/+5
| | | | llvm-svn: 328864
* [Hexagon] Add support to handle bit-reverse load intrinsicsKrzysztof Parzyszek2018-03-291-24/+45
| | | | | | Patch by Sumanth Gundapaneni. llvm-svn: 328774
* [Hexagon] Add support for "new" circular buffer intrinsicsKrzysztof Parzyszek2018-03-281-7/+94
| | | | | | | | | | | | | | | | | | | These instructions have been around for a long time, but we haven't supported intrinsics for them. The "new" versions use the CSx register for the start of the buffer instead of the K field in the Mx register. We need to use pseudo instructions for these instructions until after register allocation. The problem is that these instructions allocate a M0/CS0 or M1/CS1 pair. But, we can't generate code for the CSx set-up until after register allocation when the Mx register has been fixed for the instruction. There is a related clang patch. Patch by Brendon Cahoon. llvm-svn: 328724
* [DAG, X86] Revert r327197 "Revert r327170, r327171, r327172"Nirav Dave2018-03-191-3/+1
| | | | | | | Reland ISel cycle checking improvements after simplifying node id invariant traversal and correcting typo. llvm-svn: 327898
* Revert "[DAG, X86] Revert r327197 "Revert r327170, r327171, r327172""Nirav Dave2018-03-171-1/+3
| | | | | | as it times out building test-suite on PPC. llvm-svn: 327778
* [DAG, X86] Revert r327197 "Revert r327170, r327171, r327172"Nirav Dave2018-03-171-3/+1
| | | | | | | Reland ISel cycle checking improvements after simplifying and reducing node id invariant traversal. llvm-svn: 327777
* Revert: r327172 "Correct load-op-store cycle detection analysis"Nirav Dave2018-03-101-1/+3
| | | | | | | | | | r327171 "Improve Dependency analysis when doing multi-node Instruction Selection" r328170 "[DAG] Enforce stricter NodeId invariant during Instruction selection" Reverting patch as NodeId invariant change is causing pathological increases in compile time on PPC llvm-svn: 327197
* [DAG] Enforce stricter NodeId invariant during Instruction selectionNirav Dave2018-03-091-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Instruction Selection makes use of the topological ordering of nodes by node id (a node's operands have smaller node id than it) when doing cycle detection. During selection we may violate this property as a selection of multiple nodes may induce a use dependence (and thus a node id restriction) between two unrelated nodes. If a selected node has an unselected successor this may allow us to miss a cycle in detection an invalid selection. This patch fixes this by marking all unselected successors of a selected node have negated node id. We avoid pruning on such negative ids but still can reconstruct the original id for pruning. In-tree targets have been updated to replace DAG-level replacements with ISel-level ones which enforce this property. This preemptively fixes PR36312 before triggering commit r324359 relands Reviewers: craig.topper, bogner, jyknight Subscribers: arsenm, nhaehnle, javed.absar, llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D43198 llvm-svn: 327170
* [Hexagon] Rewrite non-HVX unaligned loads as pairs of aligned onesKrzysztof Parzyszek2018-03-071-1/+63
| | | | | | | | | This is a follow-up to r325169, this time for all types, not just HVX vector types. Disable this by default, since it's not always safe. llvm-svn: 326915
* [Hexagon] Recognize more sign-extensions as inputs to 32x32-bit multiplyKrzysztof Parzyszek2018-02-271-2/+13
| | | | llvm-svn: 326263
* [NFC] fix trivial typos in comments and documentsHiroshi Inoue2018-01-261-2/+2
| | | | | | "in in" -> "in", "on on" -> "on" etc. llvm-svn: 323508
* Revert "[Hexagon] Replace EmitFunctionEntryCode with a DAG preprocessing code"Krzysztof Parzyszek2018-01-251-21/+14
| | | | | | This reverts r323374. The fix needs a different approach. llvm-svn: 323438
* [Hexagon] Replace EmitFunctionEntryCode with a DAG preprocessing codeKrzysztof Parzyszek2018-01-241-14/+21
| | | | | | | | | The code in EmitFunctionEntryCode needs to know the maximum stack alignment, but it runs very early in the selection process (before lowering). The final stack alignment may change during lowering, so the code needs to be moved to where the alignment is known. llvm-svn: 323374
* [Hexagon] Implement basic vector operations on vectors vNi1Krzysztof Parzyszek2018-01-231-125/+55
| | | | | | | | | | | In addition to that, make sure that there are no boolean vector types that are associated with multiple register classes. Specifically, remove v32i1 and v64i1 from integer register classes. These types will correspond to results of vector comparisons, and as such should belong to the vector predicate class. Having them in scalar registers as well makes legalization ambiguous. llvm-svn: 323229
* MachineFunction: Return reference from getFunction(); NFCMatthias Braun2017-12-151-2/+2
| | | | | | The Function can never be nullptr so we can return a reference. llvm-svn: 320884
* [Hexagon] Add support for Hexagon V65Krzysztof Parzyszek2017-12-111-0/+27
| | | | llvm-svn: 320404
* [RISCV] Support lowering FrameIndexAlex Bradbury2017-12-111-20/+0
| | | | | | | | | | | | | | | | Introduces the AddrFI "addressing mode", which is necessary simply because it's not possible to write a pattern that directly matches a frameindex. Ensure callee-saved registers are accessed relative to the stackpointer. This is necessary as callee-saved register spills are performed before the frame pointer is set. Move HexagonDAGToDAGISel::isOrEquivalentToAdd to SelectionDAGISel, so we can make use of it in the RISC-V backend. Differential Revision: https://reviews.llvm.org/D39848 llvm-svn: 320353
* [Hexagon] Generate HVX code for vector construction and accessKrzysztof Parzyszek2017-12-061-1/+7
| | | | | | | | | | Support for: - build vector, - extract vector element, subvector, - insert vector element, subvector, - shuffle. llvm-svn: 319901
* Recommit r317904: [Hexagon] Create HexagonISelDAGToDAG.h, NFCKrzysztof Parzyszek2017-11-101-109/+3
| | | | | | | The Windows builder did not reconstruct the HexagonGenDAGISel.inc file after the TableGen binary has changed. llvm-svn: 317921
* Revert "[Hexagon] Create HexagonISelDAGToDAG.h, NFC"Krzysztof Parzyszek2017-11-101-3/+109
| | | | | | This reverts r317904: broke Windows build. llvm-svn: 317916
* [Hexagon] Create HexagonISelDAGToDAG.h, NFCKrzysztof Parzyszek2017-11-101-109/+3
| | | | llvm-svn: 317904
* Fix MSVC 'result of 32-bit shift implicitly converted to 64 bits' warning. NFCI.Simon Pilgrim2017-10-211-2/+2
| | | | llvm-svn: 316271
* [Hexagon] Reorganize and update instruction patternsKrzysztof Parzyszek2017-10-201-5/+101
| | | | llvm-svn: 316228
* Remove unused variables. No functionality change.Benjamin Kramer2017-10-081-1/+0
| | | | llvm-svn: 315185
* [Hexagon] Switch to parameterized register classes for HVXKrzysztof Parzyszek2017-09-151-33/+6
| | | | | | | This removes the duplicate HVX instruction set for the 128-byte mode. Single instruction set now works for both modes (64- and 128-byte). llvm-svn: 313362
* [Hexagon] Add support for nontemporal loads and stores on HVXKrzysztof Parzyszek2017-07-111-14/+32
| | | | | | | | Patch by Michael Wu. Differential Revision: https://reviews.llvm.org/D35104 llvm-svn: 307671
* [Hexagon] Generate store-immediate instructions for stack objectsKrzysztof Parzyszek2017-06-131-0/+15
| | | | | | | | | Store-immediate instructions have a non-extendable offset. Since the actual offset for a stack object is not known until much later, only generate these stores when the stack size (at the time of instruction selection) is small. llvm-svn: 305305
* [Hexagon] Improve code generation for 32x32-bit multiplicationKrzysztof Parzyszek2017-05-301-102/+87
| | | | | | | | | For multiplications of 64-bit values (giving 64-bit result), detect cases where the arguments are sign-extended 32-bit values, on a per- operand basis. This will allow few patterns to match a wider variety of combinations in which extensions can occur. llvm-svn: 304223
* [Hexagon] Refactor the DAG preprocessing code, NFCKrzysztof Parzyszek2017-03-091-32/+88
| | | | | | Extract individual transformations into their own functions. llvm-svn: 297401
* [Hexagon] Propagate zext of i1 into arithmetic code in selection DAGKrzysztof Parzyszek2017-03-091-0/+96
| | | | | | | (op ... (zext i1 c) ...) -> (select c (op ... 1 ...), (op ... 0 ...)) llvm-svn: 297391
* [Hexagon] Undo shift folding where it could simplify addressing modeKrzysztof Parzyszek2017-02-241-3/+75
| | | | | | | | | | | | For example, avoid (single shift): r0 = and(##536870908,lsr(r0,#3)) r0 = memw(r1+r0<<#0) in favor of (two shifts): r0 = lsr(r0,#5) r0 = memw(r1+r0<<#2) llvm-svn: 296196
* [Hexagon] Prettify code in HexagonDAGToDAGISel::SelectKrzysztof Parzyszek2017-02-241-47/+13
| | | | llvm-svn: 296187
* [Hexagon] Give a predicate function a more meaningful nameKrzysztof Parzyszek2016-11-141-2/+2
| | | | | | | Change "orisadd" to "IsOrAdd" to follow the naming conventions, and change "isOrAdd" in the C++ code to "isOrEquivalentToAdd". llvm-svn: 286886
* [Hexagon] Separate Hexagon subreg indices for different register classesKrzysztof Parzyszek2016-11-091-3/+2
| | | | | | | | | | | For pairs of 32-bit registers: isub_lo, isub_hi. For pairs of vector registers: vsub_lo, vsub_hi. Add generic subreg indices: ps_sub_lo, ps_sub_hi, and a function HexagonRegisterInfo::getHexagonSubRegIndex(RegClass, GenericSubreg) that returns the appropriate subreg index for RegClass. llvm-svn: 286377
* Reapply r286080 with a phony change in Hexagon's CMakeLists.txtKrzysztof Parzyszek2016-11-061-188/+0
| | | | | | | | Cmake has not recognized that Hexagon.td has a new dependency in HexagonPatterns.td. All changes to that file were not visible to the build bots. llvm-svn: 286084
* Revert r286080: it breaks build botsKrzysztof Parzyszek2016-11-061-0/+188
| | | | llvm-svn: 286081
* [Hexagon] Remove redundant custom selection codeKrzysztof Parzyszek2016-11-061-188/+0
| | | | | | | | | | | | | | | | The clr/set/toggle-bit instructions (with the bit index given as an immediate operand) had both, custom selection code that generated them, and selection patterns at the same time. The selection patterns were not used, because the custom selection code was executed first. This patch removes the custom code in favor of the selection patterns. The custom code handled 64-bit registers as well with an immediate bit index, and so new patterns were added to implement that. It was also the same case for the instruction "Rd += asr(Rs, Rt)", except that the custom code did not offer any additional functionality, and was simply removed. llvm-svn: 286080
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