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* Revert "[Hexagon] Use pseudo-instructions for true/false predicate values"Krzysztof Parzyszek2015-03-181-6/+23
| | | | | | | | This reverts r232650. Missed a piece of code in the previous commit. llvm-svn: 232656
* [Hexagon] Use pseudo-instructions for true/false predicate valuesKrzysztof Parzyszek2015-03-181-23/+6
| | | | llvm-svn: 232650
* [Hexagon] Intrinsics for circular and bit-reversed loads and storesKrzysztof Parzyszek2015-03-181-0/+200
| | | | llvm-svn: 232645
* Generate bit manipulation instructions on HexagonKrzysztof Parzyszek2015-03-181-0/+149
| | | | llvm-svn: 232577
* Remove unneeded selection functions from HexagonISelDAGToDAGKrzysztof Parzyszek2015-03-171-189/+0
| | | | | | | - SelectSelect, and - SelectTruncate llvm-svn: 232569
* Selection DAG preprocessing on HexagonKrzysztof Parzyszek2015-03-171-2/+52
| | | | | | Simplify: (or (select c x 0) z) -> (select c (or x z) z) (or (select c 0 y) z) -> (select c z (or y z)) llvm-svn: 232553
* Re-commit: [hexagon] Distinguish the 'o', 'v', and 'm' inline assembly ↵Daniel Sanders2015-03-171-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | memory constraints. Summary: But still handle them the same way since I don't know how they differ on this target. No functional change intended. Reviewers: kparzysz, adasgupt Reviewed By: kparzysz, adasgupt Subscribers: colinl, llvm-commits Differential Revision: http://reviews.llvm.org/D8204 Like for the PowerPC target, I've had to add 'i' to the constraint mappings in order to pass 2007-12-17-InvokeAsm.ll. It's not clear why 'i' has historically been treated as a memory constraint. llvm-svn: 232480
* Revert r232374: [hexagon] Distinguish the 'o', 'v', and 'm' inline assembly ↵Daniel Sanders2015-03-161-3/+3
| | | | | | | | memory constraints. 2007-12-17-InvokeAsm.ll fails on the buildbot but not on my own system. Will investigate. llvm-svn: 232376
* [hexagon] Distinguish the 'o', 'v', and 'm' inline assembly memory constraints.Daniel Sanders2015-03-161-3/+3
| | | | | | | | | | | | | | | | | | Summary: But still handle them the same way since I don't know how they differ on this target. No functional change intended. Reviewers: kparzysz, adasgupt Reviewed By: kparzysz, adasgupt Subscribers: colinl, llvm-commits Differential Revision: http://reviews.llvm.org/D8204 llvm-svn: 232374
* Recommit r232027 with PR22883 fixed: Add infrastructure for support of ↵Daniel Sanders2015-03-131-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | multiple memory constraints. The operand flag word for ISD::INLINEASM nodes now contains a 15-bit memory constraint ID when the operand kind is Kind_Mem. This constraint ID is a numeric equivalent to the constraint code string and is converted with a target specific hook in TargetLowering. This patch maps all memory constraints to InlineAsm::Constraint_m so there is no functional change at this point. It just proves that using these previously unused bits in the encoding of the flag word doesn't break anything. The next patch will make each target preserve the current mapping of everything to Constraint_m for itself while changing the target independent implementation of the hook to return Constraint_Unknown appropriately. Each target will then be adapted in separate patches to use appropriate Constraint_* values. PR22883 was caused the matching operands copying the whole of the operand flags for the matched operand. This included the constraint id which needed to be replaced with the operand number. This has been fixed with a conversion function. Following on from this, matching operands also used the operand number as the constraint id. This has been fixed by looking up the matched operand and taking it from there. llvm-svn: 232165
* Revert "r232027 - Add infrastructure for support of multiple memory constraints"Hal Finkel2015-03-121-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | This (r232027) has caused PR22883; so it seems those bits might be used by something else after all. Reverting until we can figure out what else to do. Original commit message: The operand flag word for ISD::INLINEASM nodes now contains a 15-bit memory constraint ID when the operand kind is Kind_Mem. This constraint ID is a numeric equivalent to the constraint code string and is converted with a target specific hook in TargetLowering. This patch maps all memory constraints to InlineAsm::Constraint_m so there is no functional change at this point. It just proves that using these previously unused bits in the encoding of the flag word doesn't break anything. The next patch will make each target preserve the current mapping of everything to Constraint_m for itself while changing the target independent implementation of the hook to return Constraint_Unknown appropriately. Each target will then be adapted in separate patches to use appropriate Constraint_* values. llvm-svn: 232093
* Remove unused complex patterns for addressing modes on Hexagon.Krzysztof Parzyszek2015-03-121-541/+197
| | | | llvm-svn: 232057
* Add infrastructure for support of multiple memory constraints.Daniel Sanders2015-03-121-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The operand flag word for ISD::INLINEASM nodes now contains a 15-bit memory constraint ID when the operand kind is Kind_Mem. This constraint ID is a numeric equivalent to the constraint code string and is converted with a target specific hook in TargetLowering. This patch maps all memory constraints to InlineAsm::Constraint_m so there is no functional change at this point. It just proves that using these previously unused bits in the encoding of the flag word doesn't break anything. The next patch will make each target preserve the current mapping of everything to Constraint_m for itself while changing the target independent implementation of the hook to return Constraint_Unknown appropriately. Each target will then be adapted in separate patches to use appropriate Constraint_* values. Reviewers: hfinkel Reviewed By: hfinkel Subscribers: hfinkel, jholewinski, llvm-commits Differential Revision: http://reviews.llvm.org/D8171 llvm-svn: 232027
* Fix build break introduced in r231992Krzysztof Parzyszek2015-03-121-4/+2
| | | | llvm-svn: 231996
* Eliminate constant-extender profitability checks from Hexagon iselKrzysztof Parzyszek2015-03-121-33/+0
| | | | llvm-svn: 231992
* [Hexagon] Reapply r231699. Remove assumption that second operand is an ↵Colin LeMahieu2015-03-091-123/+2
| | | | | | immediate when checking if A2_tfrsi is combinable. llvm-svn: 231710
* [Hexagon] Reverting r231699Colin LeMahieu2015-03-091-2/+123
| | | | llvm-svn: 231703
* [Hexagon] Updating constant set to simpler versions.Colin LeMahieu2015-03-091-123/+2
| | | | llvm-svn: 231699
* MathExtras: Bring Count(Trailing|Leading)Ones and CountPopulation in line ↵Benjamin Kramer2015-02-121-3/+1
| | | | | | | | with countTrailingZeros Update all callers. llvm-svn: 228930
* [Hexagon] Renaming A2_addi and formatting.Colin LeMahieu2015-02-051-4/+4
| | | | llvm-svn: 228318
* [Hexagon] Simplifying some store patterns. Adding AddrGP addressing forms.Colin LeMahieu2015-02-041-0/+5
| | | | llvm-svn: 228220
* [Hexagon] Adding selection for GlobalAddress and converting [z/i]ext load ↵Colin LeMahieu2015-02-041-0/+48
| | | | | | patterns to make use of them. llvm-svn: 228184
* Migrate HexagonISelDAGToDAG to setting a subtarget pointer duringEric Christopher2015-02-021-12/+11
| | | | | | runOnMachineFunction. Update all uses of the Subtarget accordingly. llvm-svn: 227840
* [Hexagon] Deleting a lot of old variants of intrinsics and updating references.Colin LeMahieu2015-01-281-0/+10
| | | | llvm-svn: 227338
* [Hexagon] Updating muxir/ri/ii intrinsics. Setting predicate registers as ↵Colin LeMahieu2015-01-191-94/+87
| | | | | | compatible with i32 rather than doing custom type conversion. llvm-svn: 226500
* [Hexagon] Removing old versions of vsplice, valign, cl0, ct0 and updating ↵Colin LeMahieu2015-01-151-3/+3
| | | | | | references to new versions. llvm-svn: 226194
* [Hexagon] Replacing old version of convert and load f64.Colin LeMahieu2015-01-141-0/+10
| | | | llvm-svn: 226057
* [Hexagon] Adding post-increment register form stores and register-immediate ↵Colin LeMahieu2014-12-291-8/+8
| | | | | | form stores with tests. llvm-svn: 224952
* [Hexagon] Replacing the remaining postincrement stores with versions that ↵Colin LeMahieu2014-12-291-3/+3
| | | | | | have encoding bits. llvm-svn: 224951
* [Hexagon] Renaming old multiclass for removal. Adding post-increment store ↵Colin LeMahieu2014-12-291-1/+1
| | | | | | classes and instruction defs. llvm-svn: 224949
* [Hexagon] Adding remaining post-increment instruction variants. Removing ↵Colin LeMahieu2014-12-261-3/+3
| | | | | | unused classes. llvm-svn: 224868
* [Hexagon] Adding post-increment unsigned byte loads.Colin LeMahieu2014-12-261-1/+1
| | | | llvm-svn: 224867
* [Hexagon] Adding post-increment signed byte loads with tests.Colin LeMahieu2014-12-261-1/+1
| | | | llvm-svn: 224866
* [Hexagon] Adding doubleword load.Colin LeMahieu2014-12-231-2/+2
| | | | llvm-svn: 224787
* [Hexagon] Reapplying 224775 load words.Colin LeMahieu2014-12-231-6/+6
| | | | llvm-svn: 224786
* Reverting 224775 until mayLoad flag is addressed.Colin LeMahieu2014-12-231-6/+6
| | | | llvm-svn: 224783
* [Hexagon] Adding word loads.Colin LeMahieu2014-12-231-6/+6
| | | | llvm-svn: 224775
* [Hexagon] Adding signed halfword loads.Colin LeMahieu2014-12-231-2/+2
| | | | llvm-svn: 224774
* [Hexagon] Adding unsigned halfword load.Colin LeMahieu2014-12-231-1/+1
| | | | llvm-svn: 224772
* [Hexagon] Adding memb instruction. Fixing whitespace in test from 224730.Colin LeMahieu2014-12-221-2/+2
| | | | llvm-svn: 224735
* [Hexagon] Adding classes and load unsigned byte instruction, updating usages.Colin LeMahieu2014-12-221-1/+1
| | | | llvm-svn: 224730
* [Hexagon] Removing old variants of instructions and updating references.Colin LeMahieu2014-12-191-1/+1
| | | | llvm-svn: 224612
* [Hexagon] Removing old multiply defs and updating references to new versions.Colin LeMahieu2014-12-161-4/+4
| | | | llvm-svn: 224340
* [Hexagon] Adding encoding information for sign extend word instruction.Colin LeMahieu2014-12-111-2/+2
| | | | llvm-svn: 224026
* [Hexagon] Updating rr/ri 32/64 transfer encodings and adding tests.Colin LeMahieu2014-12-091-4/+4
| | | | llvm-svn: 223821
* [Hexagon] Adding word combine dot-new form and replacing old combine opcode.Colin LeMahieu2014-12-091-3/+3
| | | | llvm-svn: 223815
* [Hexagon] Updating predicate register transfers and adding tstbit to allow ↵Colin LeMahieu2014-12-091-5/+5
| | | | | | select selection. Updating ll tests with predicate transfers that previously had nop encodings. llvm-svn: 223800
* [Hexagon] Removing old def versions and replacing usages with versions that ↵Colin LeMahieu2014-12-081-12/+12
| | | | | | have encodings. llvm-svn: 223720
* [Hexagon] Updating mux_ir/ri/ii/rr with encoding bitsColin LeMahieu2014-12-051-3/+3
| | | | llvm-svn: 223515
* [Hexagon] Adding C2_mux instruction.Colin LeMahieu2014-11-251-1/+1
| | | | llvm-svn: 222784
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