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* Fix the ridiculous SubtargetFeatures API where it implicitly expects CPU name toEvan Cheng2011-06-304-7/+8
| | | | | | | | | | be the first encoded as the first feature. It then uses the CPU name to look up features / scheduling itineray even though clients know full well the CPU name being used to query these properties. The fix is to just have the clients explictly pass the CPU name! llvm-svn: 134127
* Sink SubtargetFeature and TargetInstrItineraries (renamed ↵Evan Cheng2011-06-291-2/+1
| | | | | | MCInstrItineraries) into MC. llvm-svn: 134049
* Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo.Evan Cheng2011-06-282-4/+3
| | | | llvm-svn: 134030
* Hide more details in tablegen generated MCRegisterInfo ctor function.Evan Cheng2011-06-281-2/+1
| | | | llvm-svn: 134027
* Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.incEvan Cheng2011-06-284-6/+8
| | | | llvm-svn: 134024
* Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.incEvan Cheng2011-06-275-9/+9
| | | | | | into XXXGenRegisterInfo.inc. llvm-svn: 133922
* Fix CellSPU CMakeList.txt.Rafael Espindola2011-06-241-1/+1
| | | | llvm-svn: 133792
* Fix CellSPU CMakeLists.txtEvan Cheng2011-06-241-2/+3
| | | | llvm-svn: 133787
* Starting to refactor Target to separate out code that's needed to fully describeEvan Cheng2011-06-242-4/+6
| | | | | | | | | | | | target machine from those that are only needed by codegen. The goal is to sink the essential target description into MC layer so we can start building MC based tools without needing to link in the entire codegen. First step is to refactor TargetRegisterInfo. This patch added a base class MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to separate register description from the rest of the stuff. llvm-svn: 133782
* Use set operations instead of plain lists to enumerate register classes.Jakob Stoklund Olesen2011-06-151-129/+11
| | | | | | | | | | | | This simplifies many of the target description files since it is common for register classes to be related or contain sequences of numbered registers. I have verified that this doesn't change the files generated by TableGen for ARM and X86. It alters the allocation order of MBlaze GPR and Mips FGR32 registers, but I believe the change is benign. llvm-svn: 133105
* Remove custom allocation order boilerplate that is no longer needed.Jakob Stoklund Olesen2011-06-091-136/+8
| | | | | | | | | | | | | | | | | | | | The register allocators automatically filter out reserved registers and place the callee saved registers last in the allocation order, so custom methods are no longer necessary just for that. Some targets still use custom allocation orders: ARM/Thumb: The high registers are removed from GPR in thumb mode. The NEON allocation orders prefer to use non-VFP2 registers first. X86: The GR8 classes omit AH-DH in x86-64 mode to avoid REX trouble. SystemZ: Some of the allocation orders are omitting R12 aliases without explanation. I don't understand this target well enough to fix that. It looks like all the boilerplate could be removed by reserving the right registers. llvm-svn: 132781
* Add a parameter to CCState so that it can access the MachineFunction.Eric Christopher2011-06-081-8/+8
| | | | | | | | No functional change. Part of PR6965 llvm-svn: 132763
* Have LowerOperandForConstraint handle multiple character constraints.Eric Christopher2011-06-022-3/+3
| | | | | | Part of rdar://9119939 llvm-svn: 132510
* Use the dwarf->llvm mapping to print register names in the cfiRafael Espindola2011-05-302-0/+5
| | | | | | | | directives. Fixes PR9826. llvm-svn: 132317
* Use the correct register class for Cell varargs spilling. This fixes all of theCameron Zwarich2011-05-191-1/+1
| | | | | | verifier failures in the CodeGen/CellSPU tests. llvm-svn: 131631
* Make the logic for determining function alignment more explicit. No ↵Eli Friedman2011-05-062-8/+2
| | | | | | functionality change. llvm-svn: 131012
* Fix a ton of comment typos found by codespell. Patch byChris Lattner2011-04-152-2/+2
| | | | | | Luis Felipe Strano Moraes! llvm-svn: 129558
* Move getRegPressureLimit() from TargetLoweringInfo to TargetRegisterInfo.Cameron Zwarich2011-03-072-8/+8
| | | | llvm-svn: 127175
* Allow vector shifts (shl,lshr,ashr) on SPU.Kalle Raiskila2011-03-041-48/+16
| | | | | | | | | There was a previous implementation with patterns that would have matched e.g. shl <v4i32> <i32>, but this is not valid LLVM IR so they never were selected. llvm-svn: 126998
* Allow load from constant on SPU.Kalle Raiskila2011-03-041-1/+6
| | | | | | A 'load <4 x i32>* null' crashes llc before this fix. llvm-svn: 126995
* Add branch hinting for SPU. Kalle Raiskila2011-02-284-5/+94
| | | | | | | The implemented algorithm is overly simplistic (just speculate all branches are taken)- this is work in progress. llvm-svn: 126651
* Allow targets to specify a the type of the RHS of a shift parameterized on ↵Owen Anderson2011-02-252-5/+6
| | | | | | the type of the LHS. llvm-svn: 126518
* Revert r124611 - "Keep track of incoming argument's location while emitting ↵Devang Patel2011-02-211-1/+1
| | | | | | | | | | | LiveIns." In other words, do not keep track of argument's location. The debugger (gdb) is not prepared to see line table entries for arguments. For the debugger, "second" line table entry marks beginning of function body. This requires some coordination with debugger to get this working. - The debugger needs to be aware of prolog_end attribute attached with line table entries. - The compiler needs to accurately mark prolog_end in line table entries (at -O0 and at -O1+) llvm-svn: 126155
* Use explicit add_subdirectory's for LLVM target sublibraries insteadOscar Fuentes2011-02-201-0/+2
| | | | | | | | | of testing for its presence at cmake time. This way the build automatically regenerates the makefiles when a svn update brings in a new sublibrary. llvm-svn: 126068
* Keep track of incoming argument's location while emitting LiveIns.Devang Patel2011-01-311-1/+1
| | | | llvm-svn: 124611
* Fix vector sign extend to put the source and destination types in theDavid Greene2011-01-311-3/+3
| | | | | | correct places. llvm-svn: 124601
* Null initialize a few variables flagged byTed Kremenek2011-01-231-1/+1
| | | | | | | | | | clang's -Wuninitialized-experimental warning. While these don't look like real bugs, clang's -Wuninitialized-experimental analysis is stricter than GCC's, and these fixes have the benefit of being general nice cleanups. llvm-svn: 124073
* Allow sign-extending of i8 and i16 to i128 on SPU. Kalle Raiskila2011-01-202-1/+7
| | | | llvm-svn: 123912
* Remove unused variables found by gcc-4.6's -Wunused-but-set-variable.Jeffrey Yasskin2011-01-181-9/+0
| | | | llvm-svn: 123707
* Split up RotateShift itinerary in SPU.Kalle Raiskila2011-01-172-38/+40
| | | | | | | | 'rotq*' and 'shlq*' instructions go to the odd pipeline, wheras the inter-vector equivalents 'rot*', 'shl*' go to the even. llvm-svn: 123622
* Don't crash SPU BE with memory accesses with big alignmnet.Kalle Raiskila2011-01-171-4/+4
| | | | llvm-svn: 123620
* Teach frame lowering to ignore debug values after the terminators.Jakob Stoklund Olesen2011-01-131-2/+2
| | | | llvm-svn: 123399
* Fix a thinko in 123226 that caused test failures on "other" platforms.Kalle Raiskila2011-01-111-1/+1
| | | | llvm-svn: 123229
* Add a "nop filler" pass to SPU.Kalle Raiskila2011-01-116-1/+166
| | | | | | | | | | | | | | | Filling no-ops is done just before emitting of assembly, when the instruction stream is final. No-ops are inserted to align the instructions so the dual-issue of the pipeline is utilized. This speeds up generated code with a minimum of 1% on a select set of algorithms. This pass may be redundant if the instruction scheduler and all subsequent passes that modify the instruction stream (prolog+epilog inserter, register scavenger, are there others?) are made aware of the instruction alignments. llvm-svn: 123226
* Update CMake stuffAnton Korobeynikov2011-01-101-2/+1
| | | | llvm-svn: 123171
* Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs ↵Anton Korobeynikov2011-01-108-44/+44
| | | | | | and fixes here and there. llvm-svn: 123170
* Various bits of framework needed for precise machine-level selectionAndrew Trick2010-12-245-10/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | DAG scheduling during isel. Most new functionality is currently guarded by -enable-sched-cycles and -enable-sched-hazard. Added InstrItineraryData::IssueWidth field, currently derived from ARM itineraries, but could be initialized differently on other targets. Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is active, and if so how many cycles of state it holds. Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry into the scheduler's available queue. ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to get information about it's SUnits, provides RecedeCycle for bottom-up scheduling, correctly computes scoreboard depth, tracks IssueCount, and considers potential stall cycles when checking for hazards. ScheduleDAGRRList now models machine cycles and hazards (under flags). It tracks MinAvailableCycle, drives the hazard recognizer and priority queue's ready filter, manages a new PendingQueue, properly accounts for stall cycles, etc. llvm-svn: 122541
* whitespaceAndrew Trick2010-12-241-1/+1
| | | | llvm-svn: 122539
* Flag -> Glue, the ongoing sagaChris Lattner2010-12-231-4/+4
| | | | llvm-svn: 122513
* rename MVT::Flag to MVT::Glue. "Flag" is a terrible name forChris Lattner2010-12-211-1/+1
| | | | | | | something that just glues two nodes together, even if it is sometimes used for flags. llvm-svn: 122310
* Don't feed 19 bit immediates to ILA.Kalle Raiskila2010-12-171-3/+3
| | | | | | Patch (slightly modified) by Visa Putkinen. llvm-svn: 122052
* Dont' feed ILA two inputs - it takes just one.Kalle Raiskila2010-12-091-1/+1
| | | | llvm-svn: 121372
* Handle lshr for i128 correctly on SPU also when Kalle Raiskila2010-11-291-2/+5
| | | | | | shiftamount > 7. llvm-svn: 120288
* Enable PostRA scheduling for SPU. Kalle Raiskila2010-11-292-0/+25
| | | | | | | This speeds up selected test cases with up to 5% - no slowdowns observed. llvm-svn: 120286
* Allow machine LICM to do its job on SPU.Kalle Raiskila2010-11-292-1/+9
| | | | | | | -return a sensible value for register pressure -add pattern to 'ila' instrucion llvm-svn: 120285
* Add missing i128 case.Kalle Raiskila2010-11-291-0/+3
| | | | llvm-svn: 120284
* Move more PEI-related hooks to TFIAnton Korobeynikov2010-11-274-21/+21
| | | | llvm-svn: 120229
* Use i8 as SETCC result type for i1 in SPU.Kalle Raiskila2010-11-241-4/+14
| | | | llvm-svn: 120092
* Allow for 'fcmp ogt' in SPU.Kalle Raiskila2010-11-241-2/+2
| | | | | | Fix by Visa Putkinen! llvm-svn: 120090
* Division by pow-of-2 is not cheap on SPU, do it with Kalle Raiskila2010-11-231-2/+0
| | | | | | shifts. llvm-svn: 120022
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