diff options
| author | Kalle Raiskila <kalle.raiskila@nokia.com> | 2010-11-29 14:44:28 +0000 |
|---|---|---|
| committer | Kalle Raiskila <kalle.raiskila@nokia.com> | 2010-11-29 14:44:28 +0000 |
| commit | 1ff0bfa28fa2af61e39de20d9245e9c7fe8e22cd (patch) | |
| tree | 2b547412fec70b39e142217d3a8d3fdb26e672cf /llvm/lib/Target/CellSPU | |
| parent | dc620afd1ef1ba3699bfd93a9e42ce129067c2d1 (diff) | |
| download | bcm5719-llvm-1ff0bfa28fa2af61e39de20d9245e9c7fe8e22cd.tar.gz bcm5719-llvm-1ff0bfa28fa2af61e39de20d9245e9c7fe8e22cd.zip | |
Handle lshr for i128 correctly on SPU also when
shiftamount > 7.
llvm-svn: 120288
Diffstat (limited to 'llvm/lib/Target/CellSPU')
| -rw-r--r-- | llvm/lib/Target/CellSPU/SPUInstrInfo.td | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/llvm/lib/Target/CellSPU/SPUInstrInfo.td b/llvm/lib/Target/CellSPU/SPUInstrInfo.td index 6e06e47c496..4095951c24c 100644 --- a/llvm/lib/Target/CellSPU/SPUInstrInfo.td +++ b/llvm/lib/Target/CellSPU/SPUInstrInfo.td @@ -2727,6 +2727,8 @@ multiclass RotateMaskQuadByBitCount def v8i16: ROTQMBYBIVecInst<v8i16>; def v4i32: ROTQMBYBIVecInst<v4i32>; def v2i64: ROTQMBYBIVecInst<v2i64>; + def r128: ROTQMBYBIInst<(outs GPRC:$rT), (ins GPRC:$rA, R32C:$rB), + [/*no pattern*/]>; } defm ROTQMBYBI: RotateMaskQuadByBitCount; @@ -2762,8 +2764,9 @@ multiclass RotateMaskQuadByBits defm ROTQMBI: RotateMaskQuadByBits; def : Pat<(srl GPRC:$rA, R32C:$rB), - (ROTQMBIr128 GPRC:$rA, - (SFIr32 R32C:$rB, 0))>; + (ROTQMBYBIr128 (ROTQMBIr128 GPRC:$rA, + (SFIr32 R32C:$rB, 0)), + (SFIr32 R32C:$rB, 0))>; //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~ |
