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* Remove comparison methods for MVT. The main causeDuncan Sands2008-06-082-5/+5
| | | | | | | | | | | of apint codegen failure is the DAG combiner doing the wrong thing because it was comparing MVT's using < rather than comparing the number of bits. Removing the < method makes this mistake impossible to commit. Instead, add helper methods for comparing bits and use them. llvm-svn: 52098
* Wrap MVT::ValueType in a struct to get type safetyDuncan Sands2008-06-063-149/+156
| | | | | | | | | | | | | | | | and better control the abstraction. Rename the type to MVT. To update out-of-tree patches, the main thing to do is to rename MVT::ValueType to MVT, and rewrite expressions like MVT::getSizeInBits(VT) in the form VT.getSizeInBits(). Use VT.getSimpleVT() to extract a MVT::SimpleValueType for use in switch statements (you will get an assert failure if VT is an extended value type - these shouldn't exist after type legalization). This results in a small speedup of codegen and no new testsuite failures (x86-64 linux). llvm-svn: 52044
* Add necessary 64-bit support so that gcc frontend compiles (mostly). CurrentScott Michel2008-06-025-127/+379
| | | | | | | issue is operand promotion for setcc/select... but looks like the fundamental stuff is implemented for CellSPU. llvm-svn: 51884
* Remove more iostream header includes. Needed to implement a "FlushStream"Bill Wendling2008-05-293-5/+3
| | | | | | function to flush a specified std::ostream. llvm-svn: 51705
* Add CommonLinkage; currently tentative definitionsDale Johannesen2008-05-141-2/+3
| | | | | | | | | | are represented as "weak", but there are subtle differences in some cases on Darwin, so we need both. The intent is that "common" will behave identically to "weak" unless somebody changes their target to do something else. No functional change as yet. llvm-svn: 51118
* Change target-specific classes to use more precise static types.Dan Gohman2008-05-142-3/+3
| | | | | | | This eliminates the need for several awkward casts, including the last dynamic_cast under lib/Target. llvm-svn: 51091
* Clean up the use of static and anonymous namespaces. This turned upDan Gohman2008-05-131-0/+4
| | | | | | | several things that were neither in an anonymous namespace nor static but not intended to be global. llvm-svn: 51017
* Bug fixes and updates for CellSPU, syncing up with trunk. Most notableScott Michel2008-04-307-53/+133
| | | | | | | | fixes are target-specific lowering of frame indices, fix constants generated for the FSMBI instruction, and fixing SPUTargetLowering::computeMaskedBitsFor- TargetNode(). llvm-svn: 50462
* no need to implement this method and just have it callChris Lattner2008-04-262-14/+0
| | | | | | the default impl. llvm-svn: 50311
* Drop ISD::MEMSET, ISD::MEMMOVE, and ISD::MEMCPY, which are not LegalDan Gohman2008-04-121-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | on any current target and aren't optimized in DAGCombiner. Instead of using intermediate nodes, expand the operations, choosing between simple loads/stores, target-specific code, and library calls, immediately. Previously, the code to emit optimized code for these operations was only used at initial SelectionDAG construction time; now it is used at all times. This fixes some cases where rep;movs was being used for small copies where simple loads/stores would be better. This also cleans up code that checks for alignments less than 4; let the targets make that decision instead of doing it in target-independent code. This allows x86 to use rep;movs in low-alignment cases. Also, this fixes a bug that resulted in the use of rep;stos for memsets of 0 with non-constant memory size when the alignment was at least 4. It's better to use the library in this case, which can be significantly faster when the size is large. This also preserves more SourceValue information when memory intrinsics are lowered into simple loads/stores. llvm-svn: 49572
* Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo.Evan Cheng2008-03-312-12/+0
| | | | llvm-svn: 48995
* Add explicit keywords.Dan Gohman2008-03-251-1/+1
| | | | llvm-svn: 48801
* Add more patterns to match in the integer comparison test harnesses.Scott Michel2008-03-203-9/+8
| | | | | | | | Fix bugs encountered, mostly due to range matching for immediates; the CellSPU's 10-bit immediates are sign extended, covering a larger range of unsigned values. llvm-svn: 48575
* Use PassManagerBase instead of FunctionPassManager for functionsDan Gohman2008-03-112-4/+4
| | | | | | | | that merely add passes. This allows them to be used with either FunctionPassManager or PassManager, or even with a custom new kind of pass manager. llvm-svn: 48256
* - Style cleanup in IA64ISelLowering.h: add 'virtual' keyword for consistency.Scott Michel2008-03-101-9/+7
| | | | | | | - Add test pattern matching in CellSPU's icmp32.ll test harness - Fix CellSPU fcmp.ll-generated assert. llvm-svn: 48197
* Default ISD::PREFETCH to expand.Evan Cheng2008-03-101-1/+0
| | | | llvm-svn: 48169
* Integer comparison tests for CellSPU.Scott Michel2008-03-104-75/+182
| | | | llvm-svn: 48152
* Give TargetLowering::getSetCCResultType() a parameter so that ISD::SETCC'sScott Michel2008-03-101-0/+3
| | | | | | | | return ValueType can depend its operands' ValueType. This is a cosmetic change, no functionality impacted. llvm-svn: 48145
* cell really does support cross-regclass moves, because R3 is in lots of ↵Chris Lattner2008-03-091-4/+9
| | | | | | different regclasses, and the code is not consistent when it comes to value tracking. llvm-svn: 48119
* Implement x86 support for @llvm.prefetch. It corresponds to prefetcht{0|1|2} ↵Evan Cheng2008-03-081-0/+1
| | | | | | and prefetchnta instructions. llvm-svn: 48042
* Refine Cell's i64 constant generation code to cover more constants where theScott Michel2008-03-061-7/+28
| | | | | | upper and lower 32-bits are the same (in addition to 0 and -1 previously.) llvm-svn: 47985
* - Fix support for "special" i64 immediates that can be loadedScott Michel2008-03-054-647/+361
| | | | | | | | | | | using IL, ILA, et. al. v2i64 and i64 are now supported by the select bits (SELB) instruction. - Add missing comparison operations (testcase forthcoming) - More multiclass refactoring. llvm-svn: 47973
* Add a quick and dirty "loop aligner pass". x86 uses it to align its loops to ↵Evan Cheng2008-02-281-1/+1
| | | | | | 16-byte boundaries. llvm-svn: 47703
* Change "Name" to "AsmName" in the target register info. Gee, a refactoring toolBill Wendling2008-02-261-3/+3
| | | | | | would have been a Godsend here! llvm-svn: 47625
* Merge current work back to tree to minimize diffs and drift. Major highlightsScott Michel2008-02-239-993/+1903
| | | | | | | | | | | | | | for CellSPU modifications: - SPUInstrInfo.td refactoring: "multiclass" really is _your_ friend. - Other improvements based on refactoring effort in SPUISelLowering.cpp, esp. in SPUISelLowering::PerformDAGCombine(), where zero amount shifts and rotates are now eliminiated, other scalar-to-vector-to-scalar silliness is also eliminated. - 64-bit operations are being implemented, _muldi3.c gcc runtime now compiles and generates the right code. More work still needs to be done. llvm-svn: 47532
* Fix newly-introduced 4.3 warningsAnton Korobeynikov2008-02-203-8/+8
| | | | llvm-svn: 47375
* I cannot find a libgcc function for this builtin. Therefor expanding it to ↵Andrew Lenharth2008-02-161-1/+2
| | | | | | a noop (which is how it use to be treated). If someone who knows the x86 backend better than me could tell me how to get a lock prefix on an instruction, that would be nice to complete x86 support. llvm-svn: 47213
* Rewrite tblgen handling of subtarget features soDale Johannesen2008-02-141-0/+1
| | | | | | | | | | it follows the order of the enum, not alphabetical. The motivation is to make -mattr=+ssse3,+sse41 select SSE41 as it ought to. Added "ignored" enum values of 0 to PPC and SPU to avoid compiler warnings. llvm-svn: 47143
* Fix single precision FP constants on SPU. They are actually legal,Nate Begeman2008-02-143-20/+9
| | | | | | which allows us to kill a target-specific node. llvm-svn: 47127
* Move some useful operands up into the all-targets .tdNate Begeman2008-02-141-3/+0
| | | | llvm-svn: 47115
* Simplify some logic in ComputeMaskedBits. And change ComputeMaskedBitsDan Gohman2008-02-132-2/+2
| | | | | | to pass the mask APInt by value, not by reference. llvm-svn: 47096
* don't try to avoid inserting loads when lowering FORMAL_ARGUMENTS. Chris Lattner2008-02-131-11/+3
| | | | | | DAGCombine is now quite good at zapifying them. llvm-svn: 47053
* Convert SelectionDAG::ComputeMaskedBits to use APInt instead of uint64_t.Dan Gohman2008-02-132-8/+7
| | | | | | | Add an overload that supports the uint64_t interface for use by clients that haven't been updated yet. llvm-svn: 47039
* Rename MRegisterInfo to TargetRegisterInfo.Dan Gohman2008-02-105-7/+9
| | | | llvm-svn: 46930
* It's not always safe to fold movsd into xorpd, etc. Check the alignment of ↵Evan Cheng2008-02-082-5/+8
| | | | | | the load address first to make sure it's 16 byte aligned. llvm-svn: 46893
* Move to getCALLSEQ_END to ensure CALLSEQ_END node produces a flag. This is ↵Evan Cheng2008-02-051-2/+7
| | | | | | consistent with the definition in td file. llvm-svn: 46775
* Dwarf requires variable entries to be in the source order. Right now, since ↵Evan Cheng2008-02-041-1/+0
| | | | | | we are recording variable information at isel time this means parameters would appear in the reverse order. The short term fix is to issue recordVariable() at asm printing time instead. llvm-svn: 46724
* Get rid of the annoying blank lines before labels.Evan Cheng2008-02-021-1/+0
| | | | llvm-svn: 46667
* SDIsel processes llvm.dbg.declare by recording the variable debug ↵Evan Cheng2008-02-021-0/+1
| | | | | | | | | information descriptor and its corresponding stack frame index in MachineModuleInfo. This only works if the local variable is "homed" in the stack frame. It does not work for byval parameter, etc. Added ISD::DECLARE node type to represent llvm.dbg.declare intrinsic. Now the intrinsic calls are lowered into a SDNode and lives on through out the codegen passes. For now, since all the debugging information recording is done at isel time, when a ISD::DECLARE node is selected, it has the side effect of also recording the variable. This is a short term solution that should be fixed in time. llvm-svn: 46659
* Add an extra operand to LABEL nodes which distinguishes between debug, EH, ↵Evan Cheng2008-01-311-3/+3
| | | | | | or misc labels. This fixes the EH breakage. However I am not convinced this is *the* solution. llvm-svn: 46609
* Even though InsertAtEndOfBasicBlock is an ugly hack it still deserves a ↵Evan Cheng2008-01-302-14/+0
| | | | | | | | proper name. Rename it to EmitInstrWithCustomInserter since it does not necessarily insert instruction at the end. llvm-svn: 46562
* More cleanups for CellSPU:Scott Michel2008-01-3015-458/+389
| | | | | | | | | - Expand tabs... (poss 80-col violations, will get them later...) - Consolidate logic for SelectDFormAddr and SelectDForm2Addr into a single function, simplifying maintenance. Also reduced custom instruction generation for SPUvecinsert/INSERT_MASK. llvm-svn: 46544
* Factor the addressing mode and the load/store VT out of LoadSDNodeDan Gohman2008-01-301-2/+2
| | | | | | | | and StoreSDNode into their common base class LSBaseSDNode. Member functions getLoadedVT and getStoredVT are replaced with the common getMemoryVT to simplify code that will handle both loads and stores. llvm-svn: 46538
* Overhaul Cell SPU's addressing mode internals so that there are nowScott Michel2008-01-298-680/+566
| | | | | | | | | | | | | | only two addressing mode nodes, SPUaform and SPUindirect (vice the three previous ones, SPUaform, SPUdform and SPUxform). This improves code somewhat because we now avoid using reg+reg addressing when it can be avoided. It also simplifies the address selection logic, which was the main point for doing this. Also, for various global variables that would be loaded using SPU's A-form addressing, prefer D-form offs[reg] addressing, keeping the base in a register if the variable is used more than once. llvm-svn: 46483
* Forward progress: crtbegin.c now compiles successfully!Scott Michel2008-01-174-149/+248
| | | | | | | | | | | | | Fixed CellSPU's A-form (local store) address mode, so that all globals, externals, constant pool and jump table symbols are now wrapped within a SPUISD::AFormAddr pseudo-instruction. This now identifies all local store memory addresses, although it requires a bit of legerdemain during instruction selection to properly select loads to and stores from local store, properly generating "LQA" instructions. Also added mul_ops.ll test harness for exercising integer multiplication. llvm-svn: 46142
* This commit changes:Chris Lattner2008-01-171-3/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Legalize now always promotes truncstore of i1 to i8. 2. Remove patterns and gunk related to truncstore i1 from targets. 3. Rename the StoreXAction stuff to TruncStoreAction in TLI. 4. Make the TLI TruncStoreAction table a 2d table to handle from/to conversions. 5. Mark a wide variety of invalid truncstores as such in various targets, e.g. X86 currently doesn't support truncstore of any of its integer types. 6. Add legalize support for truncstores with invalid value input types. 7. Add a dag combine transform to turn store(truncate) into truncstore when safe. The later allows us to compile CodeGen/X86/storetrunc-fp.ll to: _foo: fldt 20(%esp) fldt 4(%esp) faddp %st(1) movl 36(%esp), %eax fstps (%eax) ret instead of: _foo: subl $4, %esp fldt 24(%esp) fldt 8(%esp) faddp %st(1) fstps (%esp) movl 40(%esp), %eax movss (%esp), %xmm0 movss %xmm0, (%eax) addl $4, %esp ret llvm-svn: 46140
* rename SDTRet -> SDTNone.Chris Lattner2008-01-151-1/+1
| | | | | | Move definition of 'trap' sdnode up from x86 instrinfo to targetselectiondag.td. llvm-svn: 46017
* improve cygwin compatibility, patch by Sam BishopChris Lattner2008-01-121-1/+1
| | | | llvm-svn: 45917
* More CellSPU refinements:Scott Michel2008-01-112-15/+36
| | | | | | | | | | | | - struct_2.ll: Completely unaligned load/store testing - call_indirect.ll, struct_1.ll: Add test lines to exercise X-form [$reg($reg)] addressing At this point, loads and stores should be under control (he says in an optimistic tone of voice.) llvm-svn: 45882
* More CellSPU refinement and progress:Scott Michel2008-01-117-343/+370
| | | | | | | | | | | | | | | | | | | | - Cleaned up custom load/store logic, common code is now shared [see note below], cleaned up address modes - More test cases: various intrinsics, structure element access (load/store test), updated target data strings, indirect function calls. Note: This patch contains a refactoring of the LoadSDNode and StoreSDNode structures: they now share a common base class, LSBaseSDNode, that provides an interface to their common functionality. There is some hackery to access the proper operand depending on the derived class; otherwise, to do a proper job would require finding and rearranging the SDOperands sent to StoreSDNode's constructor. The current refactor errs on the side of being conservatively and backwardly compatible while providing functionality that reduces redundant code for targets where loads and stores are custom-lowered. llvm-svn: 45851
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