It's not always safe to fold movsd into xorpd, etc. Check the alignment of the load address first to make sure it's 16 byte aligned.

llvm-svn: 46893

2 files changed, 8 insertions, 5 deletions

diff --git a/llvm/lib/Target/CellSPU/SPUInstrInfo.cpp b/llvm/lib/Target/CellSPU/SPUInstrInfo.cpp
index ac9b9b88ff4..64f6225f707 100644
--- a/llvm/lib/Target/CellSPU/SPUInstrInfo.cpp
+++ b/llvm/lib/Target/CellSPU/SPUInstrInfo.cpp
@@ -391,9 +391,10 @@ void SPUInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
 /// foldMemoryOperand - SPU, like PPC, can only fold spills into
 /// copy instructions, turning them into load/store instructions.
 MachineInstr *
-SPUInstrInfo::foldMemoryOperand(MachineInstr *MI,
-                                   SmallVectorImpl<unsigned> &Ops,
-                                   int FrameIndex) const
+SPUInstrInfo::foldMemoryOperand(MachineFunction &MF,
+                                MachineInstr *MI,
+                                SmallVectorImpl<unsigned> &Ops,
+                                int FrameIndex) const
 {
 #if SOMEDAY_SCOTT_LOOKS_AT_ME_AGAIN
   if (Ops.size() != 1) return NULL;
diff --git a/llvm/lib/Target/CellSPU/SPUInstrInfo.h b/llvm/lib/Target/CellSPU/SPUInstrInfo.h
index 10c39a0545e..39237eef61b 100644
--- a/llvm/lib/Target/CellSPU/SPUInstrInfo.h
+++ b/llvm/lib/Target/CellSPU/SPUInstrInfo.h
@@ -77,12 +77,14 @@ namespace llvm {
                                  SmallVectorImpl<MachineInstr*> &NewMIs) const;
     
     //! Fold spills into load/store instructions
-    virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
+    virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
+                                            MachineInstr* MI,
                                             SmallVectorImpl<unsigned> &Ops,
                                             int FrameIndex) const;
 
     //! Fold any load/store to an operand
-    virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
+    virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
+                                            MachineInstr* MI,
                                             SmallVectorImpl<unsigned> &Ops,
                                             MachineInstr* LoadMI) const {
       return 0;