| Commit message (Collapse) | Author | Age | Files | Lines |
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Approved by Chris Lattner.
llvm-svn: 167984
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* wrap code blocks in \code ... \endcode;
* refer to parameter names in paragraphs correctly (\arg is not what most
people want -- it starts a new paragraph);
* use \param instead of \arg to document parameters in order to be consistent
with the rest of the codebase.
llvm-svn: 163902
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Reviewed offline by chandlerc.
llvm-svn: 162623
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llvm-svn: 148578
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llvm-svn: 144631
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When this field is true it means that the load is from constant (runt-time or compile-time) and so can be hoisted from loops or moved around other memory accesses
llvm-svn: 144100
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registeration and creation code into XXXMCDesc libraries.
llvm-svn: 135184
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A 'load <4 x i32>* null' crashes llc before this fix.
llvm-svn: 126995
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clang's -Wuninitialized-experimental warning.
While these don't look like real bugs, clang's
-Wuninitialized-experimental analysis is stricter
than GCC's, and these fixes have the benefit
of being general nice cleanups.
llvm-svn: 124073
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and fixes here and there.
llvm-svn: 123170
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DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.
Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.
Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.
Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.
ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.
ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.
llvm-svn: 122541
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llvm-svn: 121372
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llvm-svn: 120284
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llvm-svn: 119990
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llvm-svn: 115921
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Also remove some code that died in the process.
One now non-existant ori is checked for.
llvm-svn: 115306
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"getFixedStack" on the MachinePointerInfo class. While
this isn't the problem I'm setting out to solve, it is the
right way to eliminate PseudoSourceValue, so lets go with it.
llvm-svn: 114406
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This cleans up after the mess r108567 left in the CellSPU backend.
ORCvt-instruction were used to reinterpret registers, and the ORs were then
removed by isMoveInstr(). This patch now removes 350 instrucions of format:
or $3, $3, $3
(from the 52 testcases in CodeGen/CellSPU). One case of a nonexistant or is
checked for.
Some moves of the form 'ori $., $., 0' and 'ai $., $., 0' still remain.
llvm-svn: 114074
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llvm-svn: 113073
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llvm-svn: 112955
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llvm-svn: 112073
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store for "half vectors"
llvm-svn: 110198
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llvm-svn: 107127
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random load/store, rather than crashing llc.
llvm-svn: 105710
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llvm-svn: 105269
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emit an add instruction of the form 'a reg, reg, imm'."
Patch by Kalle Raiskila!
llvm-svn: 103021
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llvm-svn: 101636
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const_casts, and it reinforces the design of the Target classes being
immutable.
SelectionDAGISel::IsLegalToFold is now a static member function, because
PIC16 uses it in an unconventional way. There is more room for API
cleanup here.
And PIC16's AsmPrinter no longer uses TargetLowering.
llvm-svn: 101635
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llvm-svn: 101334
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readability.
llvm-svn: 100756
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llvm-svn: 100709
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makes calls a little bit more consistent and allows easy removal of the
specializations in the future. Convert all callers to the templated functions.
llvm-svn: 99838
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Most of these were unused, some of them were wrong and unused (isS16Constant<short>,
isS10Constant<short>).
llvm-svn: 99827
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DoInstructionSelection. Inline "SelectRoot" into it from DAGISelHeader.
Sink some other stuff out of DAGISelHeader into SDISel.
Eliminate the various 'Indent' stuff from various targets, which dates
to when isel was recursive.
17 files changed, 114 insertions(+), 430 deletions(-)
llvm-svn: 97555
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llvm-svn: 96885
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llvm-svn: 96871
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llvm-svn: 96854
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llvm-svn: 96852
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about ownership and update policies. It isn't clear why it is doing all
this lowering at isel time instead of in legalize. This fixes fcmp64.ll
llvm-svn: 96849
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change to SelectionDAG build APIs.
llvm-svn: 96232
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clear what information these functions are actually using.
This is also a micro-optimization, as passing a SDNode * around is
simpler than passing a { SDNode *, int } by value or reference.
llvm-svn: 92564
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llvm-svn: 86149
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naming scheme used in SelectionDAG, where there are multiple kinds
of "target" nodes, but "machine" nodes are nodes which represent
a MachineInstr.
llvm-svn: 82790
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code, according to Anton (I'm not totally convinced, but we can always
resurrect patches if we need to do so.)
- Start moving CellSPU's tests to prefer FileCheck.
llvm-svn: 79958
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(IBM).
llvm-svn: 79949
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llvm-svn: 79834
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infrastructure work needed to get the contexts to where they need to be first.
llvm-svn: 78759
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while
the latter is capable of representing either a primitive or an extended type.
llvm-svn: 78713
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own struct type.
llvm-svn: 78610
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shouldn't do AU.setPreservesCFG(), because even though CodeGen passes
don't modify the LLVM IR CFG, they may modify the MachineFunction CFG,
and passes like MachineLoop are registered with isCFGOnly set to true.
llvm-svn: 77691
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