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* Rename MRegisterInfo to TargetRegisterInfo.Dan Gohman2008-02-106-9/+10
| | | | llvm-svn: 46930
* It's not always safe to fold movsd into xorpd, etc. Check the alignment of ↵Evan Cheng2008-02-082-5/+8
| | | | | | the load address first to make sure it's 16 byte aligned. llvm-svn: 46893
* Re-apply the memory operand changes, with a fix for the staticDan Gohman2008-02-061-12/+8
| | | | | | | | initializer problem, a minor tweak to the way the DAGISelEmitter finds load/store nodes, and a renaming of the new PseudoSourceValue objects. llvm-svn: 46827
* Dwarf requires variable entries to be in the source order. Right now, since ↵Evan Cheng2008-02-041-1/+0
| | | | | | we are recording variable information at isel time this means parameters would appear in the reverse order. The short term fix is to issue recordVariable() at asm printing time instead. llvm-svn: 46724
* explicitly include Compiler.h instead of getting it from tblgen in the ↵Chris Lattner2008-02-031-0/+1
| | | | | | middle of a class. llvm-svn: 46676
* Get rid of the annoying blank lines before labels.Evan Cheng2008-02-021-1/+0
| | | | llvm-svn: 46667
* SDIsel processes llvm.dbg.declare by recording the variable debug ↵Evan Cheng2008-02-021-0/+1
| | | | | | | | | information descriptor and its corresponding stack frame index in MachineModuleInfo. This only works if the local variable is "homed" in the stack frame. It does not work for byval parameter, etc. Added ISD::DECLARE node type to represent llvm.dbg.declare intrinsic. Now the intrinsic calls are lowered into a SDNode and lives on through out the codegen passes. For now, since all the debugging information recording is done at isel time, when a ISD::DECLARE node is selected, it has the side effect of also recording the variable. This is a short term solution that should be fixed in time. llvm-svn: 46659
* Revert 46556 and 46585. Dan please fix the PseudoSourceValue problem and ↵Evan Cheng2008-01-311-8/+12
| | | | | | re-commit. llvm-svn: 46623
* Create a new class, MemOperand, for describing memory referencesDan Gohman2008-01-311-12/+8
| | | | | | | | | | | | | | | | in the backend. Introduce a new SDNode type, MemOperandSDNode, for holding a MemOperand in the SelectionDAG IR, and add a MemOperand list to MachineInstr, and code to manage them. Remove the offset field from SrcValueSDNode; uses of SrcValueSDNode that were using it are all all using MemOperandSDNode now. Also, begin updating some getLoad and getStore calls to use the PseudoSourceValue objects. Most of this was written by Florian Brander, some reorganization and updating to TOT by me. llvm-svn: 46585
* This commit changes:Chris Lattner2008-01-171-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Legalize now always promotes truncstore of i1 to i8. 2. Remove patterns and gunk related to truncstore i1 from targets. 3. Rename the StoreXAction stuff to TruncStoreAction in TLI. 4. Make the TLI TruncStoreAction table a 2d table to handle from/to conversions. 5. Mark a wide variety of invalid truncstores as such in various targets, e.g. X86 currently doesn't support truncstore of any of its integer types. 6. Add legalize support for truncstores with invalid value input types. 7. Add a dag combine transform to turn store(truncate) into truncstore when safe. The later allows us to compile CodeGen/X86/storetrunc-fp.ll to: _foo: fldt 20(%esp) fldt 4(%esp) faddp %st(1) movl 36(%esp), %eax fstps (%eax) ret instead of: _foo: subl $4, %esp fldt 24(%esp) fldt 8(%esp) faddp %st(1) fstps (%esp) movl 40(%esp), %eax movss (%esp), %xmm0 movss %xmm0, (%eax) addl $4, %esp ret llvm-svn: 46140
* rename SDTRet -> SDTNone.Chris Lattner2008-01-151-1/+1
| | | | | | Move definition of 'trap' sdnode up from x86 instrinfo to targetselectiondag.td. llvm-svn: 46017
* rename MachineInstr::setInstrDescriptor -> setDescChris Lattner2008-01-111-1/+1
| | | | llvm-svn: 45871
* get def use info more correct.Chris Lattner2008-01-101-1/+1
| | | | llvm-svn: 45821
* remove MachineOpCode typedef.Chris Lattner2008-01-071-1/+1
| | | | llvm-svn: 45679
* Move even more functionality from MRegisterInfo into TargetInstrInfo.Owen Anderson2008-01-074-47/+48
| | | | | | Some day I'll get it all moved over... llvm-svn: 45672
* rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate.Chris Lattner2008-01-062-2/+2
| | | | llvm-svn: 45667
* Change the 'isStore' inferrer to look for 'SDNPMayStore' Chris Lattner2008-01-062-33/+32
| | | | | | | | | | | instead of "ISD::STORE". This allows us to mark target-specific dag nodes as storing (such as ppc byteswap stores). This allows us to remove more explicit isStore flags from the .td files. Finally, add a warning for when a .td file contains an explicit isStore and tblgen is able to infer it. llvm-svn: 45654
* Change MachineRelocation::DoesntNeedFnStub to NeedStub. This fields will be usedEvan Cheng2008-01-031-1/+2
| | | | | | for non-function GV relocations that require function address stubs (e.g. Mac OS X in non-static mode). llvm-svn: 45527
* Move some more instruction creation methods from RegisterInfo into InstrInfo.Owen Anderson2008-01-014-120/+114
| | | | llvm-svn: 45484
* Fix a problem where lib/Target/TargetInstrInfo.h would include and useChris Lattner2008-01-012-2/+2
| | | | | | | | | | a header file from libcodegen. This violates a layering order: codegen depends on target, not the other way around. The fix to this is to split TII into two classes, TII and TargetInstrInfoImpl, which defines stuff that depends on libcodegen. It is defined in libcodegen, where the base is not. llvm-svn: 45475
* Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of theOwen Anderson2007-12-313-24/+28
| | | | | | Machine-level API cleanup instigated by Chris. llvm-svn: 45470
* Rename SSARegMap -> MachineRegisterInfo in keeping with the idea Chris Lattner2007-12-312-12/+11
| | | | | | | | | | | | | | that "machine" classes are used to represent the current state of the code being compiled. Given this expanded name, we can start moving other stuff into it. For now, move the UsedPhysRegs and LiveIn/LoveOuts vectors from MachineFunction into it. Update all the clients to match. This also reduces some needless #includes, such as MachineModuleInfo from MachineFunction. llvm-svn: 45467
* Add new shorter predicates for testing machine operands for various types: Chris Lattner2007-12-304-16/+14
| | | | | | | | | | | | e.g. MO.isMBB() instead of MO.isMachineBasicBlock(). I don't plan on switching everything over, so new clients should just start using the shorter names. Remove old long accessors, switching everything over to use the short accessor: getMachineBasicBlock() -> getMBB(), getConstantPoolIndex() -> getIndex(), setMachineBasicBlock -> setMBB(), etc. llvm-svn: 45464
* Use MachineOperand::getImm instead of MachineOperand::getImmedValue. ↵Chris Lattner2007-12-304-18/+16
| | | | | | Likewise setImmedValue -> setImm llvm-svn: 45453
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-2926-52/+52
| | | | llvm-svn: 45418
* remove attribution from lib Makefiles.Chris Lattner2007-12-291-2/+2
| | | | llvm-svn: 45415
* Implicit def instructions, e.g. X86::IMPLICIT_DEF_GR32, are always ↵Evan Cheng2007-12-121-0/+2
| | | | | | re-materializable and they should not be spilled. llvm-svn: 44960
* Add a argument to storeRegToStackSlot and storeRegToAddr to specify whetherEvan Cheng2007-12-052-8/+9
| | | | | | the stored register is killed. llvm-svn: 44600
* Remove redundant foldMemoryOperand variants and other code clean up.Evan Cheng2007-12-022-15/+7
| | | | llvm-svn: 44517
* Allow some reloads to be folded in multi-use cases. Specifically testl r, r ↵Evan Cheng2007-12-011-0/+12
| | | | | | -> cmpl [mem], 0. llvm-svn: 44479
* something wrong with this optAndrew Lenharth2007-11-271-12/+14
| | | | llvm-svn: 44370
* Add parameter to getDwarfRegNum to permit targetsDale Johannesen2007-11-132-2/+2
| | | | | | | | to use different mappings for EH and debug info; no functional change yet. Fix warning in X86CodeEmitter. llvm-svn: 44056
* Unifacalize the CALLSEQ{START,END} stuff.Bill Wendling2007-11-131-5/+5
| | | | llvm-svn: 44045
* Unify CALLSEQ_{START,END}. They take 4 parameters: the chain, two stackBill Wendling2007-11-132-9/+17
| | | | | | | | | | | adjustment fields, and an optional flag. If there is a "dynamic_stackalloc" in the code, make sure that it's bracketed by CALLSEQ_START and CALLSEQ_END. If not, then there is the potential for the stack to be changed while the stack's being used by another instruction (like a call). This can only result in tears... llvm-svn: 44037
* Add a flag for indirect branch instructions.Owen Anderson2007-11-121-2/+1
| | | | | | Target maintainers: please check that the instructions for your target are correctly marked. llvm-svn: 44012
* Use TableGen to emit information for dwarf register numbers. Anton Korobeynikov2007-11-113-64/+71
| | | | | | | | This makes DwarfRegNum to accept list of numbers instead. Added three different "flavours", but only slightly tested on x86-32/linux. Please check another subtargets if possible, llvm-svn: 43997
* Eliminate the remaining uses of getTypeSize. ThisDuncan Sands2007-11-051-1/+1
| | | | | | | | | | | | | | should only effect x86 when using long double. Now 12/16 bytes are output for long double globals (the exact amount depends on the alignment). This brings globals in line with the rest of LLVM: the space reserved for an object is now always the ABI size. One tricky point is that only 10 bytes should be output for long double if it is a field in a packed struct, which is the reason for the additional argument to EmitGlobalConstant. llvm-svn: 43688
* - Added getOpcodeAfterMemoryUnfold(). It doesn't unfold an instruction, but ↵Evan Cheng2007-10-182-4/+4
| | | | | | | | only returns the opcode of the instruction post unfolding. - Fix some copy+paste bugs. llvm-svn: 43153
* Use SmallVectorImpl instead of SmallVector with hardcoded size in MRegister ↵Evan Cheng2007-10-182-8/+8
| | | | | | public interface. llvm-svn: 43150
* Revert 42908 for now.Evan Cheng2007-10-141-4/+4
| | | | llvm-svn: 42960
* Change the names used for internal labels to use the currentDan Gohman2007-10-121-4/+4
| | | | | | | | | function symbol name instead of a codegen-assigned function number. Thanks Evan! :-) llvm-svn: 42908
* Set ISD::FPOW to Expand.Dan Gohman2007-10-111-1/+4
| | | | llvm-svn: 42881
* - Added a few target hooks to generate load / store instructions from / to anyEvan Cheng2007-10-052-0/+60
| | | | | | | | address (not just from / to frameindexes). - Added target hooks to unfold load / store instructions / SDNodes into separate load, data processing, store instructions / SDNodes. llvm-svn: 42621
* Allow copyRegToReg to emit cross register classes copies.Evan Cheng2007-09-262-5/+12
| | | | | | Tested with "make check"! llvm-svn: 42346
* More explicit keywords.Dan Gohman2007-09-251-1/+1
| | | | llvm-svn: 42316
* Fix PR 1681. When X86 target uses +sse -sse2,Dale Johannesen2007-09-231-0/+2
| | | | | | | | | | keep f32 in SSE registers and f64 in x87. This is effectively a new codegen mode. Change addLegalFPImmediate to permit float and double variants to do different things. Adjust callers. llvm-svn: 42246
* Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead.Evan Cheng2007-09-111-3/+3
| | | | llvm-svn: 41863
* Fold the adjust_trampoline intrinsic intoDuncan Sands2007-09-111-3/+0
| | | | | | | init_trampoline. There is now only one trampoline intrinsic. llvm-svn: 41841
* Add lengthof and endof templates that hide a lot of sizeof computations.Owen Anderson2007-09-071-1/+2
| | | | | | Patch by Sterling Stein! llvm-svn: 41758
* Enhance APFloat to retain bits of NaNs (fixes oggenc).Dale Johannesen2007-08-311-5/+5
| | | | | | | Use APFloat interfaces for more references, mostly of ConstantFPSDNode. llvm-svn: 41632
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