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| author | Evan Cheng <evan.cheng@apple.com> | 2007-12-05 03:14:33 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2007-12-05 03:14:33 +0000 |
| commit | bb26301864354b6bfc01212d4aa0ef695fbdc833 (patch) | |
| tree | 2a038c5528298d90a23e0f9d74a1a8d2078376b5 /llvm/lib/Target/Alpha | |
| parent | d766e5d7c24b517bb8e2315dfd880dc78dedaed6 (diff) | |
| download | bcm5719-llvm-bb26301864354b6bfc01212d4aa0ef695fbdc833.tar.gz bcm5719-llvm-bb26301864354b6bfc01212d4aa0ef695fbdc833.zip | |
Add a argument to storeRegToStackSlot and storeRegToAddr to specify whether
the stored register is killed.
llvm-svn: 44600
Diffstat (limited to 'llvm/lib/Target/Alpha')
| -rw-r--r-- | llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp | 13 | ||||
| -rw-r--r-- | llvm/lib/Target/Alpha/AlphaRegisterInfo.h | 4 |
2 files changed, 9 insertions, 8 deletions
diff --git a/llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp b/llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp index b8e2c268271..8185a796f76 100644 --- a/llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp +++ b/llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp @@ -61,28 +61,29 @@ AlphaRegisterInfo::AlphaRegisterInfo(const TargetInstrInfo &tii) void AlphaRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, - unsigned SrcReg, int FrameIdx, - const TargetRegisterClass *RC) const { + unsigned SrcReg, bool isKill, int FrameIdx, + const TargetRegisterClass *RC) const { //cerr << "Trying to store " << getPrettyName(SrcReg) << " to " // << FrameIdx << "\n"; //BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg); if (RC == Alpha::F4RCRegisterClass) BuildMI(MBB, MI, TII.get(Alpha::STS)) - .addReg(SrcReg, false, false, true) + .addReg(SrcReg, false, false, isKill) .addFrameIndex(FrameIdx).addReg(Alpha::F31); else if (RC == Alpha::F8RCRegisterClass) BuildMI(MBB, MI, TII.get(Alpha::STT)) - .addReg(SrcReg, false, false, true) + .addReg(SrcReg, false, false, isKill) .addFrameIndex(FrameIdx).addReg(Alpha::F31); else if (RC == Alpha::GPRCRegisterClass) BuildMI(MBB, MI, TII.get(Alpha::STQ)) - .addReg(SrcReg, false, false, true) + .addReg(SrcReg, false, false, isKill) .addFrameIndex(FrameIdx).addReg(Alpha::F31); else abort(); } void AlphaRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, + bool isKill, SmallVectorImpl<MachineOperand> &Addr, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs) const { @@ -96,7 +97,7 @@ void AlphaRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, else abort(); MachineInstrBuilder MIB = - BuildMI(TII.get(Opc)).addReg(SrcReg, false, false, true); + BuildMI(TII.get(Opc)).addReg(SrcReg, false, false, isKill); for (unsigned i = 0, e = Addr.size(); i != e; ++i) { MachineOperand &MO = Addr[i]; if (MO.isRegister()) diff --git a/llvm/lib/Target/Alpha/AlphaRegisterInfo.h b/llvm/lib/Target/Alpha/AlphaRegisterInfo.h index 04565f7bb22..7a846dcc4d7 100644 --- a/llvm/lib/Target/Alpha/AlphaRegisterInfo.h +++ b/llvm/lib/Target/Alpha/AlphaRegisterInfo.h @@ -30,10 +30,10 @@ struct AlphaRegisterInfo : public AlphaGenRegisterInfo { /// Code Generation virtual methods... void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, - unsigned SrcReg, int FrameIndex, + unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC) const; - void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, + void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, SmallVectorImpl<MachineOperand> &Addr, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs) const; |
