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* Fill out support for Thumb2 encodings of NEON instructions.Owen Anderson2010-11-113-0/+21
| | | | llvm-svn: 118854
* Add correct Thumb2 encodings for NEON vst[1,2,3,4] and vld[1,2,3,4].Owen Anderson2010-11-113-1/+22
| | | | llvm-svn: 118843
* Revert the accidental commit I made reverting the previous commit.Eric Christopher2010-11-111-6/+7
| | | | llvm-svn: 118835
* ARM fixup encoding for direct call instructions (BL).Jim Grosbach2010-11-111-8/+22
| | | | llvm-svn: 118829
* Revert this temporarily.Eric Christopher2010-11-115-104/+31
| | | | llvm-svn: 118827
* Change the prologue and epilogue to use push/pop for the low ARM registers.Eric Christopher2010-11-114-25/+97
| | | | llvm-svn: 118823
* Add support for Thumb2 encodings of NEON data processing instructions, using ↵Owen Anderson2010-11-113-0/+26
| | | | | | | | the new PostEncoderMethod infrastructure. More tests to come. llvm-svn: 118819
* Encoding of destination fixup for ARM branch and conditional branchJim Grosbach2010-11-115-13/+57
| | | | | | instructions. llvm-svn: 118801
* Encoding for ARM LDRSH_POST.Jim Grosbach2010-11-114-7/+39
| | | | llvm-svn: 118794
* Encoding for ARM LDRSH and LDRSH_PRE. Cannonicalize operand names.Jim Grosbach2010-11-112-39/+49
| | | | llvm-svn: 118767
* Fix encoding of Ra register for ARM smla* instructions.Jim Grosbach2010-11-111-6/+6
| | | | llvm-svn: 118761
* ARM STRH encoding information.Jim Grosbach2010-11-114-11/+44
| | | | llvm-svn: 118757
* Move LDM predicate operand encoding into base clase. Add STM missing STMJim Grosbach2010-11-102-10/+18
| | | | | | encoding bits. llvm-svn: 118738
* ARM LDM encoding for the mode (ia, ib, da, db) operand.Jim Grosbach2010-11-104-1/+19
| | | | llvm-svn: 118736
* Fix ARM encoding of non-return LDM instructions.Jim Grosbach2010-11-102-4/+11
| | | | llvm-svn: 118732
* Fix ARM encoding of LDM+Return instruction.Jim Grosbach2010-11-102-3/+10
| | | | llvm-svn: 118730
* Fix an issue where we tried to turn a v2f32 build_vector into a v4i32 build ↵Nate Begeman2010-11-101-2/+2
| | | | | | vector with 2 elts llvm-svn: 118720
* Simplify and clean up MC symbol lookup for ARM constant pool values. This fixesJim Grosbach2010-11-101-10/+10
| | | | | | | | double quoting of ObjC symbol names in constant pool entries. rdar://8652107 llvm-svn: 118688
* Update ARMConstantPoolValue to not use a modifier string. Use an explicitJim Grosbach2010-11-101-47/+38
| | | | | | | VariantKind marker to indicate the additional information necessary. Update MC to handle the new Kinds. rdar://8647623 llvm-svn: 118671
* Emit a '!' if this is a "writeback" register or memory address.Bill Wendling2010-11-101-2/+2
| | | | llvm-svn: 118662
* Rename a parameter to avoid confusion with a local variableMatt Beaumont-Gay2010-11-101-3/+3
| | | | llvm-svn: 118656
* Emit the warning about the register list not being in ascending order only once.Bill Wendling2010-11-091-5/+8
| | | | llvm-svn: 118653
* s/std::vector/SmallVector/Bill Wendling2010-11-091-12/+11
| | | | llvm-svn: 118648
* Delete the allocated vector.Bill Wendling2010-11-091-0/+4
| | | | llvm-svn: 118644
* Define the subtarget feature for the architecture version,Bob Wilson2010-11-091-15/+40
| | | | | | | as derived from the target triple. This is important for enabling features that are implied based on the architecture version. llvm-svn: 118643
* Do not use MEMBARRIER_MCR for any Thumb code.Bob Wilson2010-11-091-2/+2
| | | | | | | | | It is only supported for ARM code. Normally Thumb2 code would use DMB instead, but depending on how the compiler is invoked (e.g., -mattr=-db) that might be disabled. This prevents a "cannot select MEMBARRIER_MCR" error in that situation. Radar 8644195 llvm-svn: 118642
* Two types of instructions have register lists:Bill Wendling2010-11-091-56/+32
| | | | | | | | | | | * LDM, et al, uses a bit mask to indicate the register list. * VLDM, et al, uses a base register plus number. The LDM instructions may be non-contiguous, but the VLDM ones must be contiguous. Those are semantic checks that should be done later in the compiler. Also postpone the creation of the bit mask until it's needed. llvm-svn: 118640
* Change the ARMConstantPoolValue modifier string to an enumeration. This willJim Grosbach2010-11-094-17/+42
| | | | | | help in MC'izing the references that use them. llvm-svn: 118633
* Handle ARM constant pool values that need an explicit reference to the '.'Jim Grosbach2010-11-091-1/+9
| | | | | | pseudo-label. (TLS stuff). llvm-svn: 118609
* Trailing whitespace.Jim Grosbach2010-11-091-6/+6
| | | | llvm-svn: 118606
* Further MCize ARM constant pool values. This allows basic PIC references forJim Grosbach2010-11-091-67/+83
| | | | | | object file emission. llvm-svn: 118601
* Add encoding of Rt to ARM LDR/STR w/ reg+reg offset encoding.Jim Grosbach2010-11-091-0/+2
| | | | llvm-svn: 118600
* For ARM load/store instructions, encode [reg+reg] with no shifter immediate asJim Grosbach2010-11-091-0/+3
| | | | | | a left shift by zero. llvm-svn: 118587
* ARM .word data fixups don't need an adjustment.Jim Grosbach2010-11-091-0/+1
| | | | llvm-svn: 118586
* Add encoder method for ARM load/store shifted register offset operands.Jim Grosbach2010-11-093-1/+48
| | | | llvm-svn: 118513
* Add support for a few simple fixups to the ARM Darwin asm backend. This allowsJim Grosbach2010-11-092-10/+36
| | | | | | | | | | | | | | constant pool references and global variable refernces to resolve properly for object file generation. For example, int x; void foo(unsigned a, unsigned *p) { p[a] = x; } can now be successfully compiled directly to an (ARM mode) object file. llvm-svn: 118469
* Revert r118457 and r118458. These won't hold for GPRs.Bill Wendling2010-11-092-6/+8
| | | | llvm-svn: 118462
* Get the register and count from the register list operands.Bill Wendling2010-11-081-8/+5
| | | | llvm-svn: 118458
* reglist has two operands.Bill Wendling2010-11-081-0/+1
| | | | llvm-svn: 118457
* The "addRegListOperands()" function returns the start register and the totalBill Wendling2010-11-081-15/+21
| | | | | | number of registers in the list. llvm-svn: 118456
* Add support for ARM's specialized vector-compare-against-zero instructions.Owen Anderson2010-11-083-24/+68
| | | | llvm-svn: 118453
* Add "write back" bit encoding.Bill Wendling2010-11-081-8/+16
| | | | llvm-svn: 118446
* Revert 118422 in search of bot verdancy.Dale Johannesen2010-11-082-78/+10
| | | | llvm-svn: 118429
* Support -mcpu=cortex-a8 in ARM attributes - Has Fixme. 1 Test modified.Jason W Kim2010-11-082-10/+78
| | | | llvm-svn: 118422
* Complete listing of ARM/MC/ELF relocation enumsJason W Kim2010-11-081-3/+134
| | | | llvm-svn: 118413
* Make RegList an ASM operand so that TableGen will generate code for it. This isBill Wendling2010-11-081-2/+7
| | | | | | an initial implementation and may change once reglists are fully fleshed out. llvm-svn: 118390
* Revert.Bill Wendling2010-11-081-1/+1
| | | | llvm-svn: 118389
* In this context, a reglist is a reg.Bill Wendling2010-11-071-1/+1
| | | | llvm-svn: 118375
* Add support for parsing register lists. We can't use a bitfield to keep track ofBill Wendling2010-11-061-22/+64
| | | | | | | | | | | the registers, because the register numbers may be much greater than the number of bits available in the machine's register. I extracted the register list verification code out of the actual parsing of the registers. This made checking for errors much easier. It also limits the number of warnings that would be emitted for cascading infractions. llvm-svn: 118363
* Return the base register of a register list for the "getReg()" method. This isBill Wendling2010-11-061-3/+8
| | | | | | | to satisfy the ClassifyOperand method of the Asm matcher without having to add a RegList type to every back-end. llvm-svn: 118360
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