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authorJim Grosbach <grosbach@apple.com>2010-11-09 17:38:15 +0000
committerJim Grosbach <grosbach@apple.com>2010-11-09 17:38:15 +0000
commit59002dc97349d41122d7a30b207a14d27ba550f2 (patch)
tree3cc328511afffe02c74f3663b4e06f19680f7c77 /llvm/lib/Target/ARM
parent9b973490c91f79530630586d31a75946905c2cec (diff)
downloadbcm5719-llvm-59002dc97349d41122d7a30b207a14d27ba550f2.tar.gz
bcm5719-llvm-59002dc97349d41122d7a30b207a14d27ba550f2.zip
For ARM load/store instructions, encode [reg+reg] with no shifter immediate as
a left shift by zero. llvm-svn: 118587
Diffstat (limited to 'llvm/lib/Target/ARM')
-rw-r--r--llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp3
1 files changed, 3 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp b/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp
index 7b0bf12bffc..bd799f233c0 100644
--- a/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp
+++ b/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp
@@ -277,6 +277,9 @@ getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
// ROR - 11
switch (ShOp) {
default: llvm_unreachable("Unknown shift opc!");
+ case ARM_AM::no_shift:
+ assert(ShImm == 0 && "Non-zero shift amount with no shift type!");
+ // fall through
case ARM_AM::lsl: SBits = 0x0; break;
case ARM_AM::lsr: SBits = 0x1; break;
case ARM_AM::asr: SBits = 0x2; break;
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