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* Let dwarf writer allocate extra space in the debug location expression. This ↵Devang Patel2011-04-262-5/+8
| | | | | | space, if requested, will be used for complex addresses of the Blocks' variables. llvm-svn: 130178
* Fix Target/ARM/Thumb1FrameLowering.h header guard.Sebastian Redl2011-04-241-1/+1
| | | | llvm-svn: 130097
* Thumb2 and ARM add/subtract with carry fixes.Andrew Trick2011-04-234-115/+106
| | | | | | | | | | | | | Fixes Thumb2 ADCS and SBCS lowering: <rdar://problem/9275821>. t2ADCS/t2SBCS are now pseudo instructions, consistent with ARM, so the assembly printer correctly prints the 's' suffix. Fixes Thumb2 adde -> SBC matching to check for live/dead carry flags. Fixes the internal ARM machine opcode mnemonic for ADCS/SBCS. Fixes ARM SBC lowering to check for live carry (potential bug). llvm-svn: 130048
* whitespaceAndrew Trick2011-04-231-6/+6
| | | | llvm-svn: 130046
* Disassembly of A8.6.59 LDR (literal) Encoding T1 (16-bit thumb instruction) ↵Johnny Chen2011-04-221-0/+13
| | | | | | | | | | should print out ldr, not ldr.n. rdar://problem/9267772 llvm-svn: 130008
* Add asserts.Devang Patel2011-04-221-0/+2
| | | | llvm-svn: 129995
* In Thumb2 mode, lower frame indix references to:Evan Cheng2011-04-222-9/+13
| | | | | | | | | | | add <rd>, sp, #<imm8> ldr <rd>, [sp, #<imm8>] When the offset from sp is multiple of 4 and in range of 0-1020. This saves code size by utilizing 16-bit instructions. rdar://9321541 llvm-svn: 129971
* Fix DWARF description of Q registers.Devang Patel2011-04-211-0/+27
| | | | llvm-svn: 129952
* Fix DWARF description of S registers.Devang Patel2011-04-212-0/+44
| | | | llvm-svn: 129947
* As per ARM docs, register Dx is described as DW_OP_regx(256+x) in DWARF.Devang Patel2011-04-211-24/+32
| | | | llvm-svn: 129922
* Remove -use-divmod-libcall. Let targets opt in when they are available.Evan Cheng2011-04-202-1/+4
| | | | llvm-svn: 129884
* Prefer cheap registers for busy live ranges.Jakob Stoklund Olesen2011-04-201-0/+3
| | | | | | | | | | | | | | On the x86-64 and thumb2 targets, some registers are more expensive to encode than others in the same register class. Add a CostPerUse field to the TableGen register description, and make it available from TRI->getCostPerUse. This represents the cost of a REX prefix or a 32-bit instruction encoding required by choosing a high register. Teach the greedy register allocator to prefer cheap registers for busy live ranges (as indicated by spill weight). llvm-svn: 129864
* Excise unintended hunk in 129858. <rdar://problem/7662569>Stuart Hastings2011-04-201-5/+0
| | | | llvm-svn: 129862
* ARM byval support. Will be enabled by another patch to the FE. ↵Stuart Hastings2011-04-203-80/+173
| | | | | | <rdar://problem/7662569> llvm-svn: 129858
* Fix typo in the comment.Johnny Chen2011-04-191-1/+1
| | | | llvm-svn: 129837
* ADT/Triple: Move a variety of clients to using isOSDarwin() and isOSWindows()Daniel Dunbar2011-04-193-21/+18
| | | | | | predicates. llvm-svn: 129816
* Remove some duplicate op action entries and reorganize.Eric Christopher2011-04-191-8/+5
| | | | llvm-svn: 129781
* This patch combines several changes from Evan Cheng for rdar://8659675.Bob Wilson2011-04-195-12/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Making use of VFP / NEON floating point multiply-accumulate / subtraction is difficult on current ARM implementations for a few reasons. 1. Even though a single vmla has latency that is one cycle shorter than a pair of vmul + vadd, a RAW hazard during the first (4? on Cortex-a8) can cause additional pipeline stall. So it's frequently better to single codegen vmul + vadd. 2. A vmla folowed by a vmul, vmadd, or vsub causes the second fp instruction to stall for 4 cycles. We need to schedule them apart. 3. A vmla followed vmla is a special case. Obvious issuing back to back RAW vmla + vmla is very bad. But this isn't ideal either: vmul vadd vmla Instead, we want to expand the second vmla: vmla vmul vadd Even with the 4 cycle vmul stall, the second sequence is still 2 cycles faster. Up to now, isel simply avoid codegen'ing fp vmla / vmls. This works well enough but it isn't the optimial solution. This patch attempts to make it possible to use vmla / vmls in cases where it is profitable. A. Add missing isel predicates which cause vmla to be codegen'ed. B. Make sure the fmul in (fadd (fmul)) has a single use. We don't want to compute a fmul and a fmla. C. Add additional isel checks for vmla, avoid cases where vmla is feeding into fp instructions (except for the #3 exceptional case). D. Add ARM hazard recognizer to model the vmla / vmls hazards. E. Add a special pre-regalloc case to expand vmla / vmls when it's likely the vmla / vmls will trigger one of the special hazards. Enable these fp vmlx codegen changes for Cortex-A9. llvm-svn: 129775
* Add -mcpu=cortex-a9-mp. It's cortex-a9 with MP extension. rdar://8648637.Bob Wilson2011-04-191-0/+2
| | | | llvm-svn: 129774
* Avoid some 's' 16-bit instruction which partially update CPSRBob Wilson2011-04-194-86/+182
| | | | | | | (and add false dependency) when it isn't dependent on last CPSR defining instruction. rdar://8928208 llvm-svn: 129773
* Avoid write-after-write issue hazards for Cortex-A9.Bob Wilson2011-04-192-0/+25
| | | | | | | | | | | Add a avoidWriteAfterWrite() target hook to identify register classes that suffer from write-after-write hazards. For those register classes, try to avoid writing the same register in two consecutive instructions. This is currently disabled by default. We should not spill to avoid hazards! The command line flag -avoid-waw-hazard can be used to enable waw avoidance. llvm-svn: 129772
* Some single-precision VFP instructions can execute in either the VPF or NeonBob Wilson2011-04-191-0/+24
| | | | | | pipelines, at least on Cortex-A9. llvm-svn: 129771
* Improvements for the Cortex-A9 scheduling itineraries.Bob Wilson2011-04-191-12/+16
| | | | llvm-svn: 129770
* Change A9 scheduling itineraries VLD* / VST* entries default to "aligned". ThatEvan Cheng2011-04-192-172/+373
| | | | | | | | | is, it assumes addresses are 64-bit aligned (which should be the more common case). If the alignment is found not to be aligned, then getOperandLatency() would adjust the operand latency computation by one to compensate for it. rdar://9294833 llvm-svn: 129742
* Do not lose mem_operands while lowering VLD / VST intrinsics.Evan Cheng2011-04-192-4/+37
| | | | llvm-svn: 129738
* Trim a few unneeded includes.Jim Grosbach2011-04-183-31/+0
| | | | llvm-svn: 129723
* Small fix to the ARM AsmParser to ensure that aSean Callanan2011-04-181-0/+1
| | | | | | superclass variable is instantiated properly. llvm-svn: 129713
* Correct result when a branch condition is live across a blockStuart Hastings2011-04-161-4/+10
| | | | | | boundary. <rdar://problem/8933028> llvm-svn: 129634
* Thumb2 BFC was insufficiently encoded.Johnny Chen2011-04-152-1/+3
| | | | | | rdar://problem/9292717 llvm-svn: 129619
* A8.6.315 VLD3 (single 3-element structure to all lanes)Johnny Chen2011-04-151-0/+6
| | | | | | | | The a bit must be encoded as 0. rdar://problem/9292625 llvm-svn: 129618
* Add ORR and EOR to the CMP peephole optimizer. It's hard to get isel to generateCameron Zwarich2011-04-151-1/+9
| | | | | | a case involving EOR, so I only added a test for ORR. llvm-svn: 129610
* The AND instruction leaves the V flag unmodified, so it falls victim to the sameCameron Zwarich2011-04-151-7/+6
| | | | | | problem as all of the other instructions we fold with CMPs. llvm-svn: 129602
* Add missing register forms of instructions to the ARM CMP-folding code. ThisCameron Zwarich2011-04-151-0/+12
| | | | | | fixes <rdar://problem/9287901>. llvm-svn: 129599
* Fix a ton of comment typos found by codespell. Patch byChris Lattner2011-04-1510-14/+14
| | | | | | Luis Felipe Strano Moraes! llvm-svn: 129558
* Fix another fcopysign lowering bug. If src is f64 and destination is f32, don'tEvan Cheng2011-04-151-1/+4
| | | | | | forget to right shift the source by 32 first. rdar://9287902 llvm-svn: 129556
* For t2BFI, both Inst{26} and Inst{5} "should" be 0.Johnny Chen2011-04-151-0/+4
| | | | | Ref: I.1 Instruction encoding diagrams and pseudocode llvm-svn: 129552
* The ARM disassembler did not handle the alignment correctly for VLD*DUP* ↵Johnny Chen2011-04-151-0/+27
| | | | | | | | instructions (single element or n-element structure to all lanes). llvm-svn: 129550
* Follow up on r127913. Fix Thumb revsh isel. rdar://9286766Evan Cheng2011-04-141-1/+9
| | | | llvm-svn: 129548
* Add sanity checkings for Thumb2 Load/Store Register Exclusive family of ↵Johnny Chen2011-04-141-4/+41
| | | | | | operations. llvm-svn: 129531
* Thumb disassembler did not handle tBRIND (indirect branch) properly.Johnny Chen2011-04-131-6/+10
| | | | | | rdar://problem/9280370 llvm-svn: 129480
* Check for unallocated instruction encodings when disassembling Thumb Branch ↵Johnny Chen2011-04-131-5/+11
| | | | | | | | instructions (tBcc and t2Bcc). rdar://problem/9280470 llvm-svn: 129471
* The LDR*T/STR*T (unpriviledged load/store) operations don't take SP or PC as Rt.Johnny Chen2011-04-132-8/+16
| | | | | | rdar://problem/9279440 llvm-svn: 129469
* Fix a typo in an ARM-specific DAG combine. This fixes <rdar://problem/9278274>.Cameron Zwarich2011-04-131-1/+1
| | | | llvm-svn: 129468
* Check the corner cases for t2LDRSHi12 correctly and mark invalid encodings ↵Johnny Chen2011-04-131-1/+33
| | | | | | | | as such. rdar://problem/9276651 llvm-svn: 129462
* Fix a bug where for t2MOVCCi disassembly, the TIED_TO register operand was ↵Johnny Chen2011-04-131-3/+11
| | | | | | | | not properly handled. rdar://problem/9276427 llvm-svn: 129456
* Forgot to add this change for ↵Johnny Chen2011-04-131-4/+4
| | | | | | http://llvm.org/viewvc/llvm-project?view=rev&revision=129387. llvm-svn: 129451
* Fix a typo.Cameron Zwarich2011-04-132-7/+7
| | | | llvm-svn: 129429
* Add sanity check for Ld/St Dual forms of Thumb2 instructions.Johnny Chen2011-04-121-0/+29
| | | | | | rdar://problem/9273947 llvm-svn: 129411
* Add @earlyclobber constraints to the writeback register of all ARM store ↵Jakob Stoklund Olesen2011-04-122-12/+24
| | | | | | | | | | instructions. The ARMARM specifies these instructions as unpredictable when storing the writeback register. This shouldn't affect code generation much since storing a pointer to itself is quite rare. llvm-svn: 129409
* The Thumb2 RFE instructions need to have their second halfword fully specified.Johnny Chen2011-04-122-6/+11
| | | | | | | | | | In addition, the base register is not rGPR, but GPR with th exception that: if n == 15 then UNPREDICTABLE rdar://problem/9273836 llvm-svn: 129391
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