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* Workaround for bug 8721.Jason W Kim2011-01-111-0/+106
| | | | | | .s Test added. llvm-svn: 123292
* Clean up ARM subtarget code by using Triple ADT.Evan Cheng2011-01-116-13/+15
| | | | llvm-svn: 123276
* McARM: Fill in GetMnemonicAcceptInfo().Daniel Dunbar2011-01-111-2/+17
| | | | llvm-svn: 123253
* Fix a comment: We now have intrinsics for vcvtr.Bob Wilson2011-01-111-1/+0
| | | | llvm-svn: 123246
* McARM: Sketch some logic for determining when to add carry set and ↵Daniel Dunbar2011-01-111-4/+48
| | | | | | predication code operands based on the "canonical mnemonic". llvm-svn: 123239
* McARM: Add more hard coded logic to SplitMnemonicAndCC to also split out theDaniel Dunbar2011-01-111-11/+32
| | | | | | | | | | carry setting flag from the mnemonic. Note that this currently involves me disabling a number of working cases in arm_instructions.s, this is a hopefully short term evil which will be rapidly fixed (and greatly surpassed), assuming my current approach flies. llvm-svn: 123238
* Even if we don't have 7 bytes of stack space we may need to save andEric Christopher2011-01-111-1/+8
| | | | | | | | restore the stack pointer from the frame pointer on thumbv6. Fixes rdar://8819685 llvm-svn: 123196
* Expand on the safeness of restoring the sp from the fp a bit more.Eric Christopher2011-01-101-1/+2
| | | | llvm-svn: 123193
* McARM: Flush out hard coded known non-predicated mnemonic list.Daniel Dunbar2011-01-101-3/+12
| | | | llvm-svn: 123189
* McARM: Mark some T2 ...s instructions as codegen only, they aren't realDaniel Dunbar2011-01-101-4/+4
| | | | | | instructions but are restricted pseudo forms. llvm-svn: 123177
* ARM/MC: Mark several '...S' instructions as codegen only, they aren't realDaniel Dunbar2011-01-101-4/+6
| | | | | | instructions but are restricted pseudo forms. llvm-svn: 123176
* MC/ARM/AsmParser: Minor nitty fixes.Daniel Dunbar2011-01-101-3/+3
| | | | llvm-svn: 123175
* Update CMake stuffAnton Korobeynikov2011-01-101-2/+2
| | | | llvm-svn: 123171
* Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs ↵Anton Korobeynikov2011-01-1012-74/+76
| | | | | | and fixes here and there. llvm-svn: 123170
* MC/ARM/AsmParser: Split out SplitMnemonicAndCC().Daniel Dunbar2011-01-101-17/+29
| | | | llvm-svn: 123169
* Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic.Jakob Stoklund Olesen2011-01-103-4/+3
| | | | | | | | These functions not longer assert when passed 0, but simply return false instead. No functional change intended. llvm-svn: 123155
* Recognize inline asm 'rev /bin/bash, ' as a bswap intrinsic call.Evan Cheng2011-01-083-1/+35
| | | | llvm-svn: 123048
* Do not model all INLINEASM instructions as having unmodelled side effects.Evan Cheng2011-01-071-1/+1
| | | | | | | | | | Instead encode llvm IR level property "HasSideEffects" in an operand (shared with IsAlignStack). Added MachineInstrs::hasUnmodeledSideEffects() to check the operand when the instruction is an INLINEASM. This allows memory instructions to be moved around INLINEASM instructions. llvm-svn: 123044
* Add an explanatory message for an assertion.Bob Wilson2011-01-071-1/+2
| | | | llvm-svn: 123042
* Eliminate variable only used in debug builds.Matt Beaumont-Gay2011-01-071-3/+1
| | | | llvm-svn: 123040
* Lower some BUILD_VECTORS using VEXT+shuffle.Bob Wilson2011-01-072-2/+137
| | | | | | Patch by Tim Northover. llvm-svn: 123035
* Add ARM patterns to match EXTRACT_SUBVECTOR nodes.Bob Wilson2011-01-072-1/+18
| | | | | | | | | | | | | | | Also fix an off-by-one in SelectionDAGBuilder that was preventing shuffle vectors from being translated to EXTRACT_SUBVECTOR. Patch by Tim Northover. The test changes are needed to keep those spill-q tests from testing aligned spills and restores. If the only aligned stack objects are spill slots, we no longer realign the stack frame. Prior to this patch, an EXTRACT_SUBVECTOR was legalized by loading from the stack, which created an aligned frame index. Now, however, there is nothing except the spill slot in the stack frame, so I added an aligned alloca. llvm-svn: 122995
* PR8921: LDM/POP do not support interworking prior to v5t.Bob Wilson2011-01-062-2/+3
| | | | llvm-svn: 122970
* Remove extra whitespace.Bob Wilson2011-01-061-2/+2
| | | | llvm-svn: 122969
* Fix comment typo.Bob Wilson2011-01-061-1/+1
| | | | llvm-svn: 122968
* Re-implement r122936 with proper target hooks. Now getMaxStoresPerMemcpyEvan Cheng2011-01-061-1/+2
| | | | | | | etc. takes an option OptSize. If OptSize is true, it would return the inline limit for functions with attribute OptSize. llvm-svn: 122952
* fix some -Wself-assign warnings.Chris Lattner2011-01-051-3/+3
| | | | llvm-svn: 122893
* Fix the ARM IIC_iCMPsi itinerary and add an important assert.Andrew Trick2011-01-042-1/+3
| | | | llvm-svn: 122794
* Formatting changes. No functionality change.Bill Wendling2011-01-031-80/+77
| | | | llvm-svn: 122789
* Model operand restrictions of mul-like instructions on ARMv5 viaAnton Korobeynikov2011-01-014-10/+100
| | | | | | | | | earlyclobber stuff. This should fix PRs 2313 and 8157. Unfortunately, no testcase, since it'd be dependent on register assignments. llvm-svn: 122663
* CMake: Add disabling optimization on MSVC8 and MSVC10 as workaround for some ↵NAKAMURA Takumi2010-12-292-2/+10
| | | | | | files in Target/ARM and Target/X86. llvm-svn: 122623
* Various bits of framework needed for precise machine-level selectionAndrew Trick2010-12-246-16/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | DAG scheduling during isel. Most new functionality is currently guarded by -enable-sched-cycles and -enable-sched-hazard. Added InstrItineraryData::IssueWidth field, currently derived from ARM itineraries, but could be initialized differently on other targets. Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is active, and if so how many cycles of state it holds. Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry into the scheduler's available queue. ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to get information about it's SUnits, provides RecedeCycle for bottom-up scheduling, correctly computes scoreboard depth, tracks IssueCount, and considers potential stall cycles when checking for hazards. ScheduleDAGRRList now models machine cycles and hazards (under flags). It tracks MinAvailableCycle, drives the hazard recognizer and priority queue's ready filter, manages a new PendingQueue, properly accounts for stall cycles, etc. llvm-svn: 122541
* whitespaceAndrew Trick2010-12-244-5/+5
| | | | llvm-svn: 122539
* Use a StringSwitch<> instead of a manually constructed string matcher.Jim Grosbach2010-12-241-10/+7
| | | | llvm-svn: 122530
* Remove dead patterns.Jim Grosbach2010-12-231-26/+0
| | | | llvm-svn: 122524
* Recognize a few more documented register name aliases for ARM in the asm lexer.Jim Grosbach2010-12-231-0/+18
| | | | llvm-svn: 122523
* Radar 8803471: Fix expansion of ARM BCCi64 pseudo instructions.Bob Wilson2010-12-231-0/+3
| | | | | | | | If the basic block containing the BCCi64 (or BCCZi64) instruction ends with an unconditional branch, that branch needs to be deleted before appending the expansion of the BCCi64 to the end of the block. llvm-svn: 122521
* Flag -> Glue, the ongoing sagaChris Lattner2010-12-233-19/+19
| | | | llvm-svn: 122513
* Trailing whitespace.Jim Grosbach2010-12-221-15/+15
| | | | llvm-svn: 122456
* Add ARM-specific DAG combining to cast i64 vector element load/stores to f64.Bob Wilson2010-12-211-5/+103
| | | | | | | | | | | Type legalization splits up i64 values into pairs of i32 values, which leads to poor quality code when inserting or extracting i64 vector elements. If the vector element is loaded or stored, it can be treated as an f64 value and loaded or stored directly from a VPR register. Use the pre-legalization DAG combiner to cast those vector elements to f64 types so that the type legalizer won't mess them up. Radar 8755338. llvm-svn: 122319
* Arm and thumb call instructions are also in different orders.Eric Christopher2010-12-211-13/+24
| | | | | | Fixes rdar://8782223 llvm-svn: 122313
* rename MVT::Flag to MVT::Glue. "Flag" is a terrible name forChris Lattner2010-12-212-10/+10
| | | | | | | something that just glues two nodes together, even if it is sometimes used for flags. llvm-svn: 122310
* If we're not using reg+reg offset we're using reg+imm, set the opcodeEric Christopher2010-12-211-2/+2
| | | | | | | | | to be the one we want to use. bugpoint reduced testcase is a little large, I'll see if I can simplify it down more. Fixes part of rdar://8782207 llvm-svn: 122307
* Fix a copy-pasto. When the tBR_JTr instruction was converted to using theBill Wendling2010-12-211-1/+1
| | | | | | | | | tPseudoInst class, its size was changed from "special" to "2 bytes". This is incorrect because the jump table will no longer be taken into account when calculating branch offsets. <rdar://problem/8782216> llvm-svn: 122303
* Comment cleanups.Bill Wendling2010-12-211-2/+2
| | | | llvm-svn: 122302
* Remove the MCObjectFormat class.Rafael Espindola2010-12-181-12/+0
| | | | llvm-svn: 122147
* Move some data to the TargetWriter.Rafael Espindola2010-12-181-6/+5
| | | | llvm-svn: 122134
* r120333 changed the opcode for the Thumb1 stuff from ARM::tMOVr toBill Wendling2010-12-181-1/+1
| | | | | | | | | | | ARM::tMOVgpr2gpr. But this check didn't change. As a result, we were getting misaligned references to the jump table from an ADR instruction. There is a test case, but unfortunately it's sensitive to random code changes. <rdar://problem/8782223> llvm-svn: 122131
* RemoveUnusedCPEntries can change things. Track it.Bill Wendling2010-12-181-1/+1
| | | | llvm-svn: 122129
* Rearrange some Neon multiclasses. No functional changes.Bob Wilson2010-12-181-74/+76
| | | | llvm-svn: 122119
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