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| author | Andrew Trick <atrick@apple.com> | 2011-01-04 00:32:57 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2011-01-04 00:32:57 +0000 |
| commit | 163a24420ad77d4e702c49d29c1d16254a4a17e2 (patch) | |
| tree | 482cee0ed5bfd8252dac4d1cb1a70a2f5c78e402 /llvm/lib/Target/ARM | |
| parent | 44e7df67d963de48125873d82eed90821c8a370d (diff) | |
| download | bcm5719-llvm-163a24420ad77d4e702c49d29c1d16254a4a17e2.tar.gz bcm5719-llvm-163a24420ad77d4e702c49d29c1d16254a4a17e2.zip | |
Fix the ARM IIC_iCMPsi itinerary and add an important assert.
llvm-svn: 122794
Diffstat (limited to 'llvm/lib/Target/ARM')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMScheduleA9.td | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMSubtarget.cpp | 1 |
2 files changed, 3 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMScheduleA9.td b/llvm/lib/Target/ARM/ARMScheduleA9.td index eab6b98a846..a9632be61f2 100644 --- a/llvm/lib/Target/ARM/ARMScheduleA9.td +++ b/llvm/lib/Target/ARM/ARMScheduleA9.td @@ -123,7 +123,8 @@ def CortexA9Itineraries : ProcessorItineraries< InstrItinData<IIC_iCMPr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1], [A9_LdBypass, A9_LdBypass]>, - InstrItinData<IIC_iCMPsi , [InstrStage<2, [A9_ALU0, A9_ALU1]>], + InstrItinData<IIC_iCMPsi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, + InstrStage<2, [A9_ALU0, A9_ALU1]>], [1, 1], [A9_LdBypass, NoBypass]>, InstrItinData<IIC_iCMPsr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, InstrStage<3, [A9_ALU0, A9_ALU1]>], diff --git a/llvm/lib/Target/ARM/ARMSubtarget.cpp b/llvm/lib/Target/ARM/ARMSubtarget.cpp index 6290e676758..2b53cfd9734 100644 --- a/llvm/lib/Target/ARM/ARMSubtarget.cpp +++ b/llvm/lib/Target/ARM/ARMSubtarget.cpp @@ -240,6 +240,7 @@ void ARMSubtarget::computeIssueWidth() { // clear the lowest bit allStage1Units ^= allStage1Units & ~(allStage1Units - 1); } + assert(InstrItins.IssueWidth <= 2 && "itinerary bug, too many stage 1 units"); } bool ARMSubtarget::enablePostRAScheduler( |
