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* Specify fixed bit in the LDRBT encoding, which allows us to distinguish it ↵Owen Anderson2011-08-121-1/+3
| | | | | | from certain USAT16 encodings. llvm-svn: 137494
* Fix decoding of pre-indexed stores.Owen Anderson2011-08-122-0/+43
| | | | llvm-svn: 137487
* Separate decoding for STREXD and LDREXD to make each work better.Owen Anderson2011-08-122-7/+24
| | | | llvm-svn: 137476
* Silence a bunch (but not all) "variable written but not read" warningsDuncan Sands2011-08-123-4/+5
| | | | | | when building with assertions disabled. llvm-svn: 137460
* ARM vector compare to zero instruction assembly parsing support.Jim Grosbach2011-08-111-0/+15
| | | | llvm-svn: 137389
* Remove no-longer-true comments. These are for the assembler, also.Jim Grosbach2011-08-111-52/+24
| | | | llvm-svn: 137375
* ARM STRT assembly parsing and encoding.Jim Grosbach2011-08-112-14/+30
| | | | llvm-svn: 137372
* Make the USAT16 operand decoder auto-generate-able.Owen Anderson2011-08-111-2/+2
| | | | llvm-svn: 137371
* Add another accidentally omitted predicate operand.Owen Anderson2011-08-111-0/+2
| | | | llvm-svn: 137370
* Add missing predicate operand on SMLA and friends.Owen Anderson2011-08-111-0/+2
| | | | llvm-svn: 137368
* ARM load shifted register pre-index fix shift value asm parser encoding.Jim Grosbach2011-08-111-1/+1
| | | | llvm-svn: 137367
* Handle new register classes in Thumb2 mode. Should fix the ARM buildbots.Owen Anderson2011-08-111-2/+4
| | | | llvm-svn: 137364
* Making SEL decodings auto-generate-able.Owen Anderson2011-08-111-2/+2
| | | | llvm-svn: 137363
* Tidy up comment.Jim Grosbach2011-08-111-2/+1
| | | | llvm-svn: 137359
* Fix decoding support for STREXD and LDREXD.Owen Anderson2011-08-112-2/+29
| | | | llvm-svn: 137356
* ARM STRH assembly parsing and encoding.Jim Grosbach2011-08-113-18/+60
| | | | llvm-svn: 137353
* Fix decoding for indexed STRB and LDRB. Fixes <rdar://problem/9926161>.Owen Anderson2011-08-111-0/+4
| | | | llvm-svn: 137347
* Tidy up. Remove unused template parameter.Jim Grosbach2011-08-112-11/+11
| | | | llvm-svn: 137345
* Improve operand validation for Thumb2 addressing modes.Owen Anderson2011-08-111-48/+50
| | | | llvm-svn: 137344
* ARM STRD assembly parsing and encoding.Jim Grosbach2011-08-113-62/+54
| | | | llvm-svn: 137342
* Continue to tighten decoding by performing more operand validation.Owen Anderson2011-08-113-2/+75
| | | | llvm-svn: 137340
* Tidy up.Jim Grosbach2011-08-111-1/+0
| | | | llvm-svn: 137339
* ARM STRBT assembly parsing and encoding.Jim Grosbach2011-08-112-25/+37
| | | | llvm-svn: 137337
* ARM STR(immediate) assembly parsing and encoding.Jim Grosbach2011-08-112-3/+22
| | | | llvm-svn: 137331
* Tighten decoding of addrmode2 instructions to reject more UNPREDICTABLE cases.Owen Anderson2011-08-111-0/+2
| | | | llvm-svn: 137325
* Tighten operand decoding of addrmode2 instruction. The offset register ↵Owen Anderson2011-08-112-2/+2
| | | | | | cannot be PC. llvm-svn: 137323
* Correct immediate range for shifter operands. Patch by James Molloy, with ↵Owen Anderson2011-08-112-4/+17
| | | | | | additional encoding fixes added by me. llvm-svn: 137322
* Improve error checking in the new ARM disassembler. Patch by James Molloy.Owen Anderson2011-08-111-116/+159
| | | | llvm-svn: 137320
* ARM push of a single register encodes as pre-indexed STR.Jim Grosbach2011-08-112-0/+23
| | | | | | | Per the ARM ARM, a 'push' of a single register encodes as an STR, not an STM. llvm-svn: 137318
* ARM pop of a single register encodes as post-indexed LDR.Jim Grosbach2011-08-112-0/+38
| | | | | | | Per the ARM ARM, a 'pop' of a single register encodes as an LDR, not an LDM. llvm-svn: 137316
* ARM LDRT assembly parsing and encoding.Jim Grosbach2011-08-102-23/+24
| | | | llvm-svn: 137282
* Tidy up. 80 columns.Jim Grosbach2011-08-101-16/+18
| | | | llvm-svn: 137277
* ARM LDRH(immediate) assembly parsing and encoding support.Jim Grosbach2011-08-102-5/+24
| | | | llvm-svn: 137260
* ARM LDRD(register) assembly parsing and encoding.Jim Grosbach2011-08-102-3/+79
| | | | | | Add support for literal encoding of #-0 along the way. llvm-svn: 137254
* Fix typo. Not quite sure how that slipped in there.Jim Grosbach2011-08-101-3/+3
| | | | llvm-svn: 137245
* ARM LDRD(immediate) assembly parsing and encoding support.Jim Grosbach2011-08-102-7/+104
| | | | llvm-svn: 137244
* Add initial support for decoding NEON instructions in Thumb2 mode.Owen Anderson2011-08-102-4/+56
| | | | llvm-svn: 137236
* Tabs --> spaces.Owen Anderson2011-08-101-2/+2
| | | | llvm-svn: 137225
* Cleanups based on Nick Lewycky's feedback.Owen Anderson2011-08-101-19/+22
| | | | llvm-svn: 137224
* Rewrite some ARM InstrInfo functions to be most accepting of arbitrary ↵Owen Anderson2011-08-101-110/+115
| | | | | | register subclasses. Hopefully this fixes some buildbots. llvm-svn: 137223
* Add support for the R and Q constraints.Rafael Espindola2011-08-101-2/+22
| | | | llvm-svn: 137217
* Push GPRnopc through a large number of instruction definitions to tighten ↵Owen Anderson2011-08-102-87/+110
| | | | | | operand decoding. llvm-svn: 137189
* Promote VMOVS to VMOVD when possible.Jakob Stoklund Olesen2011-08-091-2/+29
| | | | | | | | | | | | | | | | | | | | | | | | | On Cortex-A8, we use the NEON v2f32 instructions for f32 arithmetic. For better latency, we also send D-register copies down the NEON pipeline by translating them to vorr instructions. This patch promotes even S-register copies to D-register copies when possible so they can also go down the NEON pipeline. Example: vldr.32 s0, LCPI0_0 loop: vorr d1, d0, d0 loop2: ... vadd.f32 d1, d1, d16 The vorr instruction looked like this after regalloc: %S2<def> = COPY %S0, %D1<imp-def> Copies involving odd S-registers, and copies that don't define the full D-register are left alone. llvm-svn: 137182
* Tighten operand checking of register-shifted-register operands.Owen Anderson2011-08-092-5/+5
| | | | llvm-svn: 137180
* Tighten operand checking on memory barrier instructions.Owen Anderson2011-08-092-2/+25
| | | | llvm-svn: 137176
* Tighten operand checking on CPS instructions.Owen Anderson2011-08-092-0/+7
| | | | llvm-svn: 137172
* Create a new register class for the set of all GPRs except the PC. Use it ↵Owen Anderson2011-08-093-3/+21
| | | | | | to tighten our decoding of BFI. llvm-svn: 137168
* ARM Disassembler: sign extend branch immediates.Benjamin Kramer2011-08-091-2/+2
| | | | | | Not sure about BLXi, but this is what the old disassembler did. llvm-svn: 137156
* Silence an false-positive warning.Owen Anderson2011-08-091-1/+1
| | | | llvm-svn: 137154
* Don't generate the old-style disassembler in CMake builds either.Owen Anderson2011-08-091-1/+0
| | | | llvm-svn: 137153
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