diff options
| author | Owen Anderson <resistor@mac.com> | 2011-08-09 23:33:27 +0000 |
|---|---|---|
| committer | Owen Anderson <resistor@mac.com> | 2011-08-09 23:33:27 +0000 |
| commit | 92b942b1b533f0c26232b055e129cea21ae5e563 (patch) | |
| tree | ea8fec4e8c2e6c7c3dab1e958f6f9b274e61410f /llvm/lib/Target/ARM | |
| parent | 72323966c8d0f9584befac832dbcc328679fad48 (diff) | |
| download | bcm5719-llvm-92b942b1b533f0c26232b055e129cea21ae5e563.tar.gz bcm5719-llvm-92b942b1b533f0c26232b055e129cea21ae5e563.zip | |
Tighten operand checking of register-shifted-register operands.
llvm-svn: 137180
Diffstat (limited to 'llvm/lib/Target/ARM')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrInfo.td | 6 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 4 |
2 files changed, 5 insertions, 5 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td index e7a6b89e7b1..0cbb7650370 100644 --- a/llvm/lib/Target/ARM/ARMInstrInfo.td +++ b/llvm/lib/Target/ARM/ARMInstrInfo.td @@ -439,7 +439,7 @@ def so_reg_reg : Operand<i32>, // reg reg imm let PrintMethod = "printSORegRegOperand"; let DecoderMethod = "DecodeSORegRegOperand"; let ParserMatchClass = ShiftedRegAsmOperand; - let MIOperandInfo = (ops GPR, GPR, i32imm); + let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm); } def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; } @@ -2541,9 +2541,9 @@ def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm, let Inst{15-12} = Rd; } -def MOVsr : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_reg:$src), +def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src), DPSoRegRegFrm, IIC_iMOVsr, - "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_reg:$src)]>, + "mov", "\t$Rd, $src", [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP { bits<4> Rd; bits<12> src; diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index 4e7e582c610..59bed8ddcef 100644 --- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -683,8 +683,8 @@ static bool DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val, unsigned Rs = fieldFromInstruction32(Val, 8, 4); // Register-register - DecodeGPRRegisterClass(Inst, Rm, Address, Decoder); - DecodeGPRRegisterClass(Inst, Rs, Address, Decoder); + if (!DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)) return false; + if (!DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)) return false; ARM_AM::ShiftOpc Shift = ARM_AM::lsl; switch (type) { |
