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* [ARM64] Increases the Sched Model accuracy for Cortex-A53.Chad Rosier2014-05-166-51/+228
| | | | | | | Patch by Dave Estes <cestes@codeaurora.org> http://reviews.llvm.org/D3769 llvm-svn: 209001
* [ARM64] Fix wrong comment in load/store optimization pass.Tilmann Scheller2014-05-161-1/+1
| | | | | | | | | | | | | | | | ldr x1, [x0, #64] add x0, x0, #64 -> ldr x1, [x0], #64 is not a valid transformation, the correct transformation (and what the code actually does) is: ldr x1, [x0, #64] add x0, x0, #64 -> ldr x1, [x0, #64]! llvm-svn: 208998
* Revert "Implement global merge optimization for global variables."Rafael Espindola2014-05-162-18/+0
| | | | | | | | | | | | This reverts commit r208934. The patch depends on aliases to GEPs with non zero offsets. That is not supported and fairly broken. The good news is that GlobalAlias is being redesigned and will have support for offsets, so this patch should be a nice match for it. llvm-svn: 208978
* TableGen: fix operand counting for aliasesTim Northover2014-05-162-70/+5
| | | | | | | | | | | | | | | | | | | | | TableGen has a fairly dubious heuristic to decide whether an alias should be printed: does the alias have lest operands than the real instruction. This is bad enough (particularly with no way to override it), but it should at least be calculated consistently for both strings. This patch implements that logic: first get the *correct* string for the variant, in the same way as the Matcher, without guessing; then count the number of whitespace chars. There are basically 4 changes this brings about after the previous commits; all of these appear to be good, so I have changed the tests: + ARM64: we print "neg X, Y" instead of "sub X, xzr, Y". + ARM64: we skip implicit "uxtx" and "uxtw" modifiers. + Sparc: we print "mov A, B" instead of "or %g0, A, B". + Sparc: we print "fcmpX A, B" instead of "fcmpX %fcc0, A, B" llvm-svn: 208969
* ARM64: disable printing of "fcmXY ..., #0" aliasesTim Northover2014-05-161-2/+2
| | | | | | | | | The canonical syntax is "fcmXY ..., #0.0". This will be tested when the TableGen "should I print this Alias" heuristic is fixed (very soon). llvm-svn: 208968
* ARM64: disable printing of swapped compare-mask aliasesTim Northover2014-05-161-12/+12
| | | | | | | | | | You can perform (say) an fcmle operation by swapping the operands on an fcmge, but it shouldn't be printed like that. This will be tested when the TableGen "should I print this Alias" heuristic is fixed (very soon). llvm-svn: 208961
* ARM64: disable printing of LDUR -> LDR aliasesTim Northover2014-05-161-24/+40
| | | | | | | | | | We accept "ldr w3, [x1, #-1]" as a convenience, but we should still print the canonical "ldur" form. This will be tested when the TableGen "should I print this Alias" heuristic is fixed (very soon). llvm-svn: 208960
* ARM64: give TST aliases priority over ANDS.Tim Northover2014-05-161-10/+10
| | | | | | | | | | If an ANDS instruction has Rd == ZR it should be printed as TST since its only effect is on the flags register NZCV. This will be tested when the TableGen "should I print this Alias" heuristic is fixed (very soon). llvm-svn: 208959
* ARM64: give MOV priority over shorter ORR when printing aliases.Tim Northover2014-05-161-11/+17
| | | | | | | | | MOV is almost always the right thing to print if possile. People understand it. This will be tested when the TableGen "should I print this Alias" heuristic is fixed (very soon). llvm-svn: 208958
* ARM64: give NEG priority over SUB when printing aliases.Tim Northover2014-05-162-23/+21
| | | | | | | | | | For example, the full instruction "sub w0, wzr, w1, uxtw" could print as either "neg w0, w1" or "sub w0, wzr, w1". The former is better. This will be tested when the TableGen "should I print this Alias" heuristic is fixed (very soon). llvm-svn: 208957
* ARM64: disable printing of "lslv" type aliasesTim Northover2014-05-161-1/+1
| | | | | | | | | | You can write "lslv w0, w1, w2" (probably for legacy reasons), but it should be printed as simply "lsl". This will be tested when the TableGen "should I print this Alias" heuristic is fixed (very soon). llvm-svn: 208956
* [ARM64]Implement NEON post-increment LD1(lane) and post-increment LD1R.Hao Liu2014-05-163-12/+148
| | | | llvm-svn: 208955
* Implement global merge optimization for global variables.Jiangning Liu2014-05-152-0/+18
| | | | | | | | | | | This commit implements two command line switches -global-merge-on-external and -global-merge-aligned, and both of them are false by default, so this optimization is disabled by default for all targets. For ARM64, some back-end behaviors need to be tuned to get this optimization further enabled. llvm-svn: 208934
* [ARM64] Improve diagnostics for Cn operands in SYS instructionsBradley Smith2014-05-151-69/+24
| | | | llvm-svn: 208902
* TableGen: use correct MIOperand when printing aliasesTim Northover2014-05-151-16/+0
| | | | | | | | | | | | | | Previously, TableGen assumed that every aliased operand consumed precisely 1 MachineInstr slot (this was reasonable because until a couple of days ago, nothing more complicated was eligible for printing). This allows a couple more ARM64 aliases to print so we can remove the special code. On the X86 side, I've gone for explicit AT&T size specifiers as the default, so turned off a few of the aliases that would have just started printing. llvm-svn: 208880
* ARM64: print correct aliases for NEON mov & mvn instructionsTim Northover2014-05-152-15/+7
| | | | | | | | In all cases, if a "mov" alias exists, it is the canonical form of the instruction. Now that TableGen can support aliases containing syntax variants, we can enable them and improve the quality of the asm output. llvm-svn: 208874
* TableGen/ARM64: print aliases even if they have syntax variants.Tim Northover2014-05-151-12/+9
| | | | | | | To get at least one use of the change (and some actual tests) in with its commit, I've enabled the AArch64 & ARM64 NEON mov aliases. llvm-svn: 208867
* ARM64: add correct vector registers during asm parsingTim Northover2014-05-152-5/+23
| | | | | | | | | Previously, we ignored the difference between V64 and V128 when parsing assembly: they both got mapped to registers in the FPR128 class. This is basically harmless at the moment because they both print and encode the same way. However, it will affect the printing of aliases. llvm-svn: 208866
* [ARM64] Improve load/store diagnostics and forbid 32-bit register addressesBradley Smith2014-05-151-2/+11
| | | | llvm-svn: 208864
* [ARM64] Parse fixed vector lanes properly so that diagnostics can be emittedBradley Smith2014-05-153-81/+92
| | | | llvm-svn: 208863
* [ARM64] Add/Fixup diagnostics for floating point immediatesBradley Smith2014-05-152-3/+18
| | | | llvm-svn: 208862
* [ARM64] Add condition code operand type such that proper diagnostics can be ↵Bradley Smith2014-05-154-32/+62
| | | | | | emitted llvm-svn: 208861
* [ARM64] Add more simple diagnostics for immediate/shift rangesBradley Smith2014-05-152-10/+25
| | | | llvm-svn: 208860
* Fix typosAlp Toker2014-05-151-2/+2
| | | | llvm-svn: 208839
* [ARM64] Support aggressive fastcc/tailcallopt breaking ABI by popping out ↵Jiangning Liu2014-05-155-101/+377
| | | | | | argument stack from callee. llvm-svn: 208837
* Rename ComputeMaskedBits to computeKnownBits. "Masked" has beenJay Foad2014-05-143-11/+11
| | | | | | inappropriate since it lost its Mask parameter in r154011. llvm-svn: 208811
* [ARM64-BE] Fix byte order of CIE and FDE frames for exception handlingChristian Pirker2014-05-141-0/+17
| | | | | | Reviewed at http://reviews.llvm.org/D3741 llvm-svn: 208792
* ARM64: remove unneeded InstPrinter hacksTim Northover2014-05-141-32/+0
| | | | | | | Now that TableGen handles aliases, these are unneeded. Hopefully more will be able to go soon. llvm-svn: 208781
* [ARM64] Fix the misleading diagnostic on bad extend amount of reg+reg ↵Kevin Qin2014-05-132-11/+8
| | | | | | | | | addressing mode. A vague diagnostic replaced the misleading one. This can fix bug 19502. llvm-svn: 208669
* Folding into CSEL when there is ZEXT between SETCC and ADDWeiming Zhao2014-05-131-3/+11
| | | | | | | | | | | Normally, patterns like (add x, (setcc cc ...)) will be folded into (csel x, x+1, not cc). However, if there is a ZEXT after SETCC, they won't be folded. This patch recognizes the ZEXT and allows the generation of CSINC. This patch fixes bug 19680. llvm-svn: 208660
* TableGen: use PrintMethods to print more aliasesTim Northover2014-05-125-37/+62
| | | | llvm-svn: 208607
* AArch64/ARM64: use InstAliases for NEON logical (imm) instructions.Tim Northover2014-05-122-72/+67
| | | | llvm-svn: 208606
* AArch64/ARM64: implement "mov $Rd, $Imm" aliases in TableGen.Tim Northover2014-05-123-58/+94
| | | | | | | | This is a slightly different approach to AArch64 (the base instruction definitions aren't quite right for that to work), but achieves the same thing and reduces C++ hackery in AsmParser. llvm-svn: 208605
* ARM64: remove dead validation code from the AsmParser.Tim Northover2014-05-121-198/+0
| | | | | | | If this code triggers, any immediate has already been validated so it can't possibly trigger a diagnostic. llvm-svn: 208564
* ARM64: merge "extend" and "shift" addressing-mode enums.Tim Northover2014-05-126-330/+241
| | | | | | | | In terms of assembly, these have too much overlap to be neatly modelled as disjoint classes: in many cases "lsl" is an acceptable alternative to either "uxtw" or "uxtx". llvm-svn: 208563
* [ARM64] Add proper bounds checking/diagnostics to logical shiftsBradley Smith2014-05-123-22/+43
| | | | llvm-svn: 208540
* [ARM64] Add diagnostics for bitfield extract/insert instructionsBradley Smith2014-05-121-19/+54
| | | | | | | | Unfortunately, since ARM64 models all these instructions as aliases, the checks need to be done at the time the alias is seen rather than during instruction validation as AArch64 does it. llvm-svn: 208529
* [ARM64] Correct more bounds checks/diagnostics for arithmetic shift operandsBradley Smith2014-05-122-10/+18
| | | | llvm-svn: 208528
* [ARM64] Move register/register MOV handling into tablegen and improve ↵Bradley Smith2014-05-124-54/+26
| | | | | | diagnostics llvm-svn: 208527
* Pass the value type to TLI::getRegisterByNameHal Finkel2014-05-112-2/+3
| | | | | | | | | | | | | We must validate the value type in TLI::getRegisterByName, because if we don't and the wrong type was used with the IR intrinsic, then we'll assert (because we won't be able to find a valid register class with which to construct the requested copy operation). For PPC64, additionally, the type information is necessary to decide between the 64-bit register and the 32-bit subregister. No functionality change. llvm-svn: 208508
* Add 'override' to getRegisterByName in *ISelLowering.hHal Finkel2014-05-111-1/+1
| | | | | | No functionality change intended. llvm-svn: 208507
* ARM64: fix SELECT_CC lowering in absence of NaNs.Tim Northover2014-05-101-8/+9
| | | | | | | | | | We were swapping the true & false results while testing for FMAX/FMIN, but not putting them back to the original state if the later checks failed. Should fix PR19700. llvm-svn: 208469
* Fix broken buildJonathan Roelofs2014-05-091-1/+1
| | | | | | ARM64 backend was missing a required_library entry. llvm-svn: 208437
* [ARM64] Add diagnostics for expected arithmetic shiftsBradley Smith2014-05-083-14/+32
| | | | llvm-svn: 208330
* [ARM64] Re-work parsing of ADD/SUB shifted immediate operandsBradley Smith2014-05-083-130/+210
| | | | | | | | | | | | The parsing of ADD/SUB shifted immediates needs to be done explicitly so that better diagnostics can be emitted, as a side effect this also removes some of the hacks in the current method of handling this operand type. Additionally remove manual CMP aliasing to ADD/SUB and use InstAlias instead. llvm-svn: 208329
* [ARM64] Ensure immediates in extend operands are in a valid rangeBradley Smith2014-05-082-4/+19
| | | | | | Also emit a more useful diagnostic when they are not. llvm-svn: 208318
* [ARM64] Check for proper immediate in shift/extend operandsBradley Smith2014-05-081-42/+58
| | | | llvm-svn: 208317
* [ARM64-BE] Teach fast-isel about how to set up sub-word stack arguments for ↵James Molloy2014-05-081-1/+7
| | | | | | | | big endian calls. SelectionDAG already knows about this, but fast-isel was ignorant. llvm-svn: 208307
* ARM64: make sure FastISel emits SSA MachineInstrsTim Northover2014-05-081-3/+4
| | | | | | We need to use a temporary register for a 2-step operation like REM. llvm-svn: 208297
* AArch64/ARM64: Port NEON post-increment load/store with 2/3/4 vectors to ↵Hao Liu2014-05-083-56/+743
| | | | | | ARM64 backend. llvm-svn: 208284
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