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* AArch64/ARM64: move ARM64 into AArch64's placeTim Northover2014-05-2417-3681/+0
| | | | | | | | | | | | | | | This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. llvm-svn: 209577
* AArch64/ARM64: remove AArch64 from tree prior to renaming ARM64.Tim Northover2014-05-242-0/+28
| | | | | | | | | | | | | | | | I'm doing this in two phases for a better "git blame" record. This commit removes the previous AArch64 backend and redirects all functionality to ARM64. It also deduplicates test-lines and removes orphaned AArch64 tests. The next step will be "git mv ARM64 AArch64" and rewire most of the tests. Hopefully LLVM is still functional, though it would be even better if no-one ever had to care because the rename happens straight afterwards. llvm-svn: 209576
* ARM64: separate load/store operands to simplify assemblerTim Northover2014-05-221-14/+25
| | | | | | | | | | | | | | | | | | | This changes ARM64 to use separate operands for each component of an address, and look for separate '[', '$Rn, ..., ']' tokens when parsing. This allows us to do away with quite a bit of special C++ code to handle monolithic "addressing modes" in the MC components. The more incremental matching of the assembler operands also allows for better diagnostics when LLVM is presented with invalid input. Most of the complexity here is with the register-offset instructions, which were extremely dodgy beforehand: even when the instruction used wM, LLVM's model had xM as an operand. We papered over this discrepancy before, but that approach doesn't work now so I split them into separate X and W variants. llvm-svn: 209425
* [ARM64-BE] Fix byte order of CIE and FDE frames for exception handlingChristian Pirker2014-05-141-0/+17
| | | | | | Reviewed at http://reviews.llvm.org/D3741 llvm-svn: 208792
* ARM64: merge "extend" and "shift" addressing-mode enums.Tim Northover2014-05-121-50/+88
| | | | | | | | In terms of assembly, these have too much overlap to be neatly modelled as disjoint classes: in many cases "lsl" is an acceptable alternative to either "uxtw" or "uxtx". llvm-svn: 208563
* AArch64/ARM64: implement remaining TLS relocations (purely MC).Tim Northover2014-04-304-10/+18
| | | | llvm-svn: 207668
* [ARM64] Fix stupid copy-pasto in ARM64MCAsmInfo.cpp - aarch64_be -> arm64_beJames Molloy2014-04-301-1/+1
| | | | llvm-svn: 207627
* [C++11] Add 'override' keywords and remove 'virtual'. Additionally add ↵Craig Topper2014-04-296-29/+31
| | | | | | 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. ARM64 edition llvm-svn: 207509
* [C++] Use 'nullptr'.Craig Topper2014-04-281-2/+2
| | | | llvm-svn: 207394
* [C++] Use 'nullptr'. Target edition.Craig Topper2014-04-252-9/+9
| | | | llvm-svn: 207197
* Spread some const around for non-mutating uses of MCSymbolData.David Blaikie2014-04-241-3/+3
| | | | | | | | I discovered this const-hole while attempting to coalesnce the Symbol and SymbolMap data structures. There's some pending issues with that, but I figured this change was easy to flush early. llvm-svn: 207124
* ARM64: support relocated "TBZ/TBNZ" instructions.Tim Northover2014-04-241-0/+2
| | | | llvm-svn: 207110
* AArch64/ARM64: support relocated ADR instructionTim Northover2014-04-241-1/+2
| | | | llvm-svn: 207109
* AArch64/ARM64: add support for :abs_gN_s: MOVZ modifiersTim Northover2014-04-243-0/+12
| | | | | | We only need assembly support, so it's fairly easy. llvm-svn: 207108
* AArch64/ARM64: disentangle the "B.CC" and "LDR lit" operandsTim Northover2014-04-245-15/+49
| | | | | | | | | | | | | These can have different relocations in ELF. In particular both: b.eq global ldr x0, global are valid, giving different relocations. The only possible way to distinguish them is via a different fixup, so the operands had to be separated throughout the backend. llvm-svn: 207105
* [ARM64] Add a big endian version of the ARM64 target machine, and update all ↵James Molloy2014-04-236-28/+61
| | | | | | | | users. This completes the porting of r202024 (cpirker "Add AArch64 big endian Target (aarch64_be)") to ARM64. llvm-svn: 206965
* Fix the assembler to print a better relocatable expression errorKevin Enderby2014-04-221-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | diagnostic that includes location information. Currently if one has this assembly: .quad (0x1234 + (4 * SOME_VALUE)) where SOME_VALUE is undefined ones gets the less than useful error message with no location information: % clang -c x.s clang -cc1as: fatal error: error in backend: expected relocatable expression With this fix one now gets a more useful error message with location information: % clang -c x.s x.s:5:8: error: expected relocatable expression .quad (0x1234 + (4 * SOME_VALUE)) ^ To do this I plumbed the SMLoc through the MCObjectStreamer EmitValue() and EmitValueImpl() interfaces so it could be used when creating the MCFixup. rdar://12391022 llvm-svn: 206906
* [Modules] Fix potential ODR violations by sinking the DEBUG_TYPEChandler Carruth2014-04-222-2/+4
| | | | | | | definition below all of the header #include lines, lib/Target/... edition. llvm-svn: 206842
* [cleanup] Lift using directives, DEBUG_TYPE definitions, and even someChandler Carruth2014-04-221-2/+2
| | | | | | | | | | | | system headers above the includes of generated '.inc' files that actually contain code. In a few targets this was already done pretty consistently, but it wasn't done *really* consistently anywhere. It is strictly cleaner IMO and necessary in a bunch of places where the DEBUG_TYPE is referenced from the generated code. Consistency with the necessary places trumps. Hopefully the build bots are OK with the movement of intrin.h... llvm-svn: 206838
* AArch64/ARM64: produce correct relocation for conditional branches.Tim Northover2014-04-161-1/+5
| | | | llvm-svn: 206391
* ARM64: use the integrated assembler on ELF.Tim Northover2014-04-161-0/+2
| | | | llvm-svn: 206378
* AArch64/ARM64: only mangle MOVZ/MOVN during encoding when neededTim Northover2014-04-151-0/+16
| | | | | | | | Sometimes we need emit the bits that would actually be a MOVN when producing a relocated MOVZ instruction (don't ask). But not always, a check which ARM64 got wrong until now. llvm-svn: 206289
* [ARM64][MC] Set the default CPU string to generic.Quentin Colombet2014-04-151-3/+1
| | | | llvm-svn: 206228
* [ARM64][MC] Set the default CPU to cyclone when initilizating the MC layer.Quentin Colombet2014-04-141-0/+6
| | | | | | | | This matches that ARM64Subtarget does for now. This is related to <rdar://problem/16573920> llvm-svn: 206211
* Fix some doc and comment typosAlp Toker2014-04-091-1/+1
| | | | llvm-svn: 205899
* [ARM64] Add a PostEncoderMethod to FCMP - the Rm field should canonically be ↵Bradley Smith2014-04-091-0/+12
| | | | | | zero but should be decoded/disassembled with any value. llvm-svn: 205883
* [ARM64] Port over the PostEncoderMethod fix for SMULH/UMULH from AArch64.Bradley Smith2014-04-091-0/+13
| | | | llvm-svn: 205877
* [ARM64] Port over the PostEncoderMethod from AArch64 for exclusive loads and ↵Bradley Smith2014-04-091-0/+15
| | | | | | stores, so the unused register fields are set to all-ones canonically but are recognised with any value. llvm-svn: 205874
* [ARM64] Remove PrefetchOp and use ARM64PRFM instead.Bradley Smith2014-04-091-58/+0
| | | | llvm-svn: 205872
* [ARM64] Move ARM64BaseInfo.{cpp,h} into a Utils/ subdirectory, a la AArch64. ↵Bradley Smith2014-04-094-2822/+1
| | | | | | These files are required in the decoder, disassembler and parser, and a layering violation was imminent. llvm-svn: 205867
* [ARM64] Copy the named immediate operand mapping logic and enums from ↵Bradley Smith2014-04-093-0/+1822
| | | | | | AArch64. AArch64's named immediate mapping and parsing is much more advanced than ARM64's. No functionality change - they're currently living side by side while I switch uses over. llvm-svn: 205866
* [ARM64] Add support for NV condition code (exists only for valid ↵Bradley Smith2014-04-091-5/+6
| | | | | | assembly/disassembly, equivilant to AL) llvm-svn: 205864
* Fixing an MSVC warning about widening the result of a 32-bit shift ↵Aaron Ballman2014-04-011-1/+1
| | | | | | implicitly. No functional change intended. llvm-svn: 205304
* Fixing warnings in the MSVC build. No functional changes intended.Aaron Ballman2014-04-011-30/+30
| | | | llvm-svn: 205301
* ARM64: uncopy/paste helper functionTim Northover2014-03-301-5/+4
| | | | | | | | | It was doing functional but highly suspect operations on bools due to the more limited shifting operands supported by memory instructions. Should fix some MSVC warnings. llvm-svn: 205134
* ARM64: Remove unused helper function, make others static.Benjamin Kramer2014-03-291-3/+3
| | | | llvm-svn: 205112
* ARM64: initial backend importTim Northover2014-03-2918-0/+4483
This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
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