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* AArch64/ARM64: move ARM64 into AArch64's placeTim Northover2014-05-245-1498/+0
| | | | | | | | | | | | | | | This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. llvm-svn: 209577
* ARM64: remove '#' from annotation of add/sub immediateTim Northover2014-05-221-1/+1
| | | | | | | The full string used to be "// =#12" for example, which looks too busy. llvm-svn: 209443
* ARM64: separate load/store operands to simplify assemblerTim Northover2014-05-222-65/+41
| | | | | | | | | | | | | | | | | | | This changes ARM64 to use separate operands for each component of an address, and look for separate '[', '$Rn, ..., ']' tokens when parsing. This allows us to do away with quite a bit of special C++ code to handle monolithic "addressing modes" in the MC components. The more incremental matching of the assembler operands also allows for better diagnostics when LLVM is presented with invalid input. Most of the complexity here is with the register-offset instructions, which were extremely dodgy beforehand: even when the instruction used wM, LLVM's model had xM as an operand. We papered over this discrepancy before, but that approach doesn't work now so I split them into separate X and W variants. llvm-svn: 209425
* [ARM64] Split tbz/tbnz into W/X register variantBradley Smith2014-05-191-12/+0
| | | | llvm-svn: 209134
* TableGen: fix operand counting for aliasesTim Northover2014-05-161-65/+0
| | | | | | | | | | | | | | | | | | | | | TableGen has a fairly dubious heuristic to decide whether an alias should be printed: does the alias have lest operands than the real instruction. This is bad enough (particularly with no way to override it), but it should at least be calculated consistently for both strings. This patch implements that logic: first get the *correct* string for the variant, in the same way as the Matcher, without guessing; then count the number of whitespace chars. There are basically 4 changes this brings about after the previous commits; all of these appear to be good, so I have changed the tests: + ARM64: we print "neg X, Y" instead of "sub X, xzr, Y". + ARM64: we skip implicit "uxtx" and "uxtw" modifiers. + Sparc: we print "mov A, B" instead of "or %g0, A, B". + Sparc: we print "fcmpX A, B" instead of "fcmpX %fcc0, A, B" llvm-svn: 208969
* TableGen: use correct MIOperand when printing aliasesTim Northover2014-05-151-16/+0
| | | | | | | | | | | | | | Previously, TableGen assumed that every aliased operand consumed precisely 1 MachineInstr slot (this was reasonable because until a couple of days ago, nothing more complicated was eligible for printing). This allows a couple more ARM64 aliases to print so we can remove the special code. On the X86 side, I've gone for explicit AT&T size specifiers as the default, so turned off a few of the aliases that would have just started printing. llvm-svn: 208880
* [ARM64] Add condition code operand type such that proper diagnostics can be ↵Bradley Smith2014-05-152-7/+0
| | | | | | emitted llvm-svn: 208861
* Fix typosAlp Toker2014-05-151-2/+2
| | | | llvm-svn: 208839
* ARM64: remove unneeded InstPrinter hacksTim Northover2014-05-141-32/+0
| | | | | | | Now that TableGen handles aliases, these are unneeded. Hopefully more will be able to go soon. llvm-svn: 208781
* TableGen: use PrintMethods to print more aliasesTim Northover2014-05-122-12/+13
| | | | llvm-svn: 208607
* ARM64: merge "extend" and "shift" addressing-mode enums.Tim Northover2014-05-121-5/+5
| | | | | | | | In terms of assembly, these have too much overlap to be neatly modelled as disjoint classes: in many cases "lsl" is an acceptable alternative to either "uxtw" or "uxtx". llvm-svn: 208563
* ARM64: refactor NEON post-indexed loads & stores (MC).Tim Northover2014-05-021-347/+348
| | | | | | | | | | | | | | | | | | | Previously, LLVM had no knowledge that these instructions actually modified their address register: fine if they never end up in CodeGen, but when I'd rather like to write some patterns for them it becomes a disaster. The change is mostly straightforward, I think the most significant design decision was to *always* put the address write-back first. This allows loads and stores to be accessed more uniformly, for example permitting the continued sharing of the InstAlias definitions. I also discovered that the custom Decode logic is no longer needed, so I removed it. No tests, because there should be no functionality change. llvm-svn: 207839
* AArch64/ARM64: print BFM instructions as BFI or BFXILTim Northover2014-05-011-0/+27
| | | | | | | The canonical form of the BFM instruction is always one of the more explicit extract or insert operations, which makes reading output much easier. llvm-svn: 207752
* [ARM64] Conditionalize CPU specific system registers on subtarget featuresBradley Smith2014-05-011-2/+2
| | | | llvm-svn: 207742
* ARM64: print fp immediates without using scientific notation.Tim Northover2014-04-301-6/+4
| | | | llvm-svn: 207669
* AArch64/ARM64: expunge CPSR from the sourcesTim Northover2014-04-302-3/+3
| | | | | | | | | | | | AArch64 does not have a CPSR register in the same way that AArch32 does. Most of its compiler-relevant roles have been taken over by the more specific NZCV register (representing just the flags set by normal instructions). Its system control functions still remain, but are now under the pseudo-register referred to as "PSTATE". They're accessed via various MRS & MSR instructions described in the reference manual. llvm-svn: 207645
* ARM64: remove duplication by templating InstPrinter methodsTim Northover2014-04-302-186/+36
| | | | | | No functional change, so no tests. llvm-svn: 207638
* ARM64: hexify printing various immediate operandsTim Northover2014-04-302-0/+7
| | | | | | | | | | This is mostly aimed at the NEON logical operations and MOVI/MVNI (since they accept weird shifts which are more naturally understandable in hex notation). Also changes BRK/HINT etc, which is probably a neutral change, but easier than the alternative. llvm-svn: 207634
* ARM64: print canonical syntax for add/sub (imm) instructions.Tim Northover2014-04-301-3/+5
| | | | | | | | | | Since these instructions only accept a 12-bit immediate, possibly shifted left by 12, the canonical syntax used by the architecture reference manual is "#N {, lsl #12 }". We should accept an immediate that has already been shifted, (e.g. Also, print a comment giving the full addend since it can be helpful. llvm-svn: 207633
* [C++11] Add 'override' keywords and remove 'virtual'. Additionally add ↵Craig Topper2014-04-291-6/+6
| | | | | | 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. ARM64 edition llvm-svn: 207509
* [ARM64] Print preferred aliases for SFBM/UBFM in InstPrinterBradley Smith2014-04-251-6/+29
| | | | llvm-svn: 207219
* [C++] Use 'nullptr'. Target edition.Craig Topper2014-04-251-5/+5
| | | | llvm-svn: 207197
* AArch64/ARM64: disentangle the "B.CC" and "LDR lit" operandsTim Northover2014-04-242-5/+3
| | | | | | | | | | | | | These can have different relocations in ELF. In particular both: b.eq global ldr x0, global are valid, giving different relocations. The only possible way to distinguish them is via a different fixup, so the operands had to be separated throughout the backend. llvm-svn: 207105
* [Modules] Fix potential ODR violations by sinking the DEBUG_TYPEChandler Carruth2014-04-221-1/+2
| | | | | | | definition below all of the header #include lines, lib/Target/... edition. llvm-svn: 206842
* ARM64: [su]xtw use W regs as inputs, not X regs.Jim Grosbach2014-04-171-4/+8
| | | | | | | | | Update the SXT[BHW]/UXTW instruction aliases and the shifted reg addressing mode handling. PR19455 and rdar://16650642 llvm-svn: 206495
* Fix abuse of StringRef on ARM64SysReg::MRSMapper::toString(Val, Valid).NAKAMURA Takumi2014-04-101-4/+4
| | | | | FIXME: Could we use SmallString here? llvm-svn: 205950
* [ARM64] Change SYS without a register to an alias to make disassembling more ↵Bradley Smith2014-04-091-5/+6
| | | | | | consistant. llvm-svn: 205898
* [ARM64] Correctly disassemble ISB operand as ISB not DBarrier.Bradley Smith2014-04-091-1/+6
| | | | llvm-svn: 205897
* [ARM64] Conditional branches must always print their condition code, even AL.Bradley Smith2014-04-091-2/+1
| | | | llvm-svn: 205894
* [ARM64] When printing a pre-indexed address with #0, the ', #0' is not optional.Bradley Smith2014-04-092-0/+33
| | | | llvm-svn: 205892
* [ARM64] Add missing shifted register MVN alias to ORNBradley Smith2014-04-091-0/+8
| | | | llvm-svn: 205891
* [ARM64] SXTW/UXTW are only valid aliases for 32-bit operations.Bradley Smith2014-04-091-1/+3
| | | | llvm-svn: 205890
* [ARM64] Fix canonicalisation of MOVs. MOV is too complex to be modelled by a ↵Bradley Smith2014-04-091-1/+33
| | | | | | dumb alias. llvm-svn: 205889
* [ARM64] Tighten up the special casing in emitting arithmetic extends. UXTW ↵Bradley Smith2014-04-091-2/+4
| | | | | | should only be translated when the instruction uses WSP, not SP. Vice versa for UXTX and 64-bit instructions. llvm-svn: 205886
* [ARM64] Add missing tlbi operands and error for extra/missing register on ↵Bradley Smith2014-04-091-0/+14
| | | | | | tlbi aliases. llvm-svn: 205876
* [ARM64] Remove PrefetchOp and use ARM64PRFM instead.Bradley Smith2014-04-091-2/+4
| | | | llvm-svn: 205872
* [ARM64] Move CPSRField and DBarrier operands over to AArch64-style ↵Bradley Smith2014-04-091-4/+11
| | | | | | disassembly and assembly. This removes the last users of namespace ARM64SYS. llvm-svn: 205869
* [ARM64] Switch the decoder, disassembler, instprinter and asmparser over to ↵Bradley Smith2014-04-092-14/+20
| | | | | | using AArch64-style system registers, and fix up test failures discovered in the process. llvm-svn: 205868
* [ARM64] Move ARM64BaseInfo.{cpp,h} into a Utils/ subdirectory, a la AArch64. ↵Bradley Smith2014-04-092-2/+2
| | | | | | These files are required in the decoder, disassembler and parser, and a layering violation was imminent. llvm-svn: 205867
* ARM64: format register strings without creating a local Twine.Tim Northover2014-03-291-5/+5
| | | | | | It was causing horrible failures on some build-bots. llvm-svn: 205105
* ARM64: change format specifier to work on 32-bit targetsTim Northover2014-03-291-1/+1
| | | | | | Existing tests were failing. llvm-svn: 205092
* [ARM64] Fix 'assert("...")' to be 'assert(0 && "...")'. Otherwise, it isChandler Carruth2014-03-291-1/+1
| | | | | | | | | | | no assert at all. ;] Some of these should probably be switched to llvm_unreachable, but I didn't want to perturb the behavior in this patch. Found by -Wstring-conversion, which I'll try to turn on in CMake builds at least as it is finding useful things. llvm-svn: 205091
* ARM64: initial backend importTim Northover2014-03-295-0/+1631
This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
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