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| author | Tim Northover <tnorthover@apple.com> | 2014-05-15 13:36:01 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2014-05-15 13:36:01 +0000 |
| commit | 60091cfeb9c827187d8877aaef600bdea3d5c17d (patch) | |
| tree | ce1f51bd66ff4da9ddcbf333e88beaf00b94dfc1 /llvm/lib/Target/ARM64/InstPrinter | |
| parent | cb7f9c40f872a2d786be318674a403b5ce5fa695 (diff) | |
| download | bcm5719-llvm-60091cfeb9c827187d8877aaef600bdea3d5c17d.tar.gz bcm5719-llvm-60091cfeb9c827187d8877aaef600bdea3d5c17d.zip | |
TableGen: use correct MIOperand when printing aliases
Previously, TableGen assumed that every aliased operand consumed precisely 1
MachineInstr slot (this was reasonable because until a couple of days ago,
nothing more complicated was eligible for printing).
This allows a couple more ARM64 aliases to print so we can remove the special
code.
On the X86 side, I've gone for explicit AT&T size specifiers as the default, so
turned off a few of the aliases that would have just started printing.
llvm-svn: 208880
Diffstat (limited to 'llvm/lib/Target/ARM64/InstPrinter')
| -rw-r--r-- | llvm/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp | 16 |
1 files changed, 0 insertions, 16 deletions
diff --git a/llvm/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp b/llvm/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp index f7b358d4f42..9ca8ce45cb7 100644 --- a/llvm/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp +++ b/llvm/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp @@ -240,14 +240,6 @@ void ARM64InstPrinter::printInst(const MCInst *MI, raw_ostream &O, printShiftedRegister(MI, 2, O); return; } - // SUBS WZR, Wn, #imm ==> CMP Wn, #imm - // SUBS XZR, Xn, #imm ==> CMP Xn, #imm - if ((Opcode == ARM64::SUBSWri && MI->getOperand(0).getReg() == ARM64::WZR) || - (Opcode == ARM64::SUBSXri && MI->getOperand(0).getReg() == ARM64::XZR)) { - O << "\tcmp\t" << getRegisterName(MI->getOperand(1).getReg()) << ", "; - printAddSubImm(MI, 2, O); - return; - } // SUBS WZR, Wn, Wm{, lshift #imm} ==> CMP Wn, Wm{, lshift #imm} // SUBS XZR, Xn, Xm{, lshift #imm} ==> CMP Xn, Xm{, lshift #imm} if ((Opcode == ARM64::SUBSWrs && MI->getOperand(0).getReg() == ARM64::WZR) || @@ -272,14 +264,6 @@ void ARM64InstPrinter::printInst(const MCInst *MI, raw_ostream &O, return; } - // ADDS WZR, Wn, #imm ==> CMN Wn, #imm - // ADDS XZR, Xn, #imm ==> CMN Xn, #imm - if ((Opcode == ARM64::ADDSWri && MI->getOperand(0).getReg() == ARM64::WZR) || - (Opcode == ARM64::ADDSXri && MI->getOperand(0).getReg() == ARM64::XZR)) { - O << "\tcmn\t" << getRegisterName(MI->getOperand(1).getReg()) << ", "; - printAddSubImm(MI, 2, O); - return; - } // ADDS WZR, Wn, Wm{, lshift #imm} ==> CMN Wn, Wm{, lshift #imm} // ADDS XZR, Xn, Xm{, lshift #imm} ==> CMN Xn, Xm{, lshift #imm} if ((Opcode == ARM64::ADDSWrs && MI->getOperand(0).getReg() == ARM64::WZR) || |
