| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | AArch64/ARM64: implement diagnosis of unpredictable loads & stores | Tim Northover | 2014-05-06 | 1 | -17/+62 |
| * | ARM64: refactor NEON post-indexed loads & stores (MC). | Tim Northover | 2014-05-02 | 1 | -571/+0 |
| * | [ARM64] Conditionalize CPU specific system registers on subtarget features | Bradley Smith | 2014-05-01 | 1 | -2/+10 |
| * | AArch64/ARM64: expunge CPSR from the sources | Tim Northover | 2014-04-30 | 1 | -9/+10 |
| * | AArch64/ARM64: disentangle the "B.CC" and "LDR lit" operands | Tim Northover | 2014-04-24 | 1 | -5/+4 |
| * | [ARM64] Add a big endian version of the ARM64 target machine, and update all ... | James Molloy | 2014-04-23 | 1 | -2/+6 |
| * | [Modules] Fix potential ODR violations by sinking the DEBUG_TYPE | Chandler Carruth | 2014-04-22 | 1 | -2/+2 |
| * | [cleanup] Lift using directives, DEBUG_TYPE definitions, and even some | Chandler Carruth | 2014-04-22 | 1 | -2/+2 |
| * | ARM64: Extended addressing mode source reg is 64-bit. | Jim Grosbach | 2014-04-21 | 1 | -5/+1 |
| * | [MC] Require an MCContext when constructing an MCDisassembler. | Lang Hames | 2014-04-15 | 1 | -2/+3 |
| * | Make helper static and place random global into the llvm namespace. | Benjamin Kramer | 2014-04-12 | 1 | -6/+5 |
| * | Remove redundant symbolization support from MCDisassembler interface. | Lang Hames | 2014-04-11 | 1 | -205/+20 |
| * | [ARM64] Flag setting logical/add/sub immediate instructions don't use SP. | Bradley Smith | 2014-04-09 | 1 | -4/+14 |
| * | [ARM64] Fix disassembly logic for extended loads/stores with 32-bit registers. | Bradley Smith | 2014-04-09 | 1 | -2/+2 |
| * | [ARM64] Ensure sp is decoded as SP, not XZR in LD1 instructions. | Bradley Smith | 2014-04-09 | 1 | -2/+2 |
| * | [ARM64] SCVTF and FCVTZS/U are undefined if scale<5> == 0. | Bradley Smith | 2014-04-09 | 1 | -6/+18 |
| * | [ARM64] Use PStateMapper to ensure that MSRcpsr operands are validated during... | Bradley Smith | 2014-04-09 | 1 | -2/+7 |
| * | [ARM64] Switch the decoder, disassembler, instprinter and asmparser over to u... | Bradley Smith | 2014-04-09 | 1 | -7/+26 |
| * | [ARM64] Move ARM64BaseInfo.{cpp,h} into a Utils/ subdirectory, a la AArch64. ... | Bradley Smith | 2014-04-09 | 1 | -1/+1 |
| * | [ARM64] Shifted register ALU ops are reserved if sf=0 and imm6<5>=1, and also... | Bradley Smith | 2014-04-09 | 1 | -9/+20 |
| * | [ARM64] STRHro and STRBro were not being decoded at all. | Bradley Smith | 2014-04-09 | 1 | -0/+2 |
| * | [ARM64] MOVK with sf=0 and hw<1>=1 is unallocated. Shift amount for ADD/SUB i... | Bradley Smith | 2014-04-09 | 1 | -0/+6 |
| * | [ARM64] Register-offset loads and stores with the 'option' field equal to 00x... | Bradley Smith | 2014-04-09 | 1 | -14/+5 |
| * | Fixing warnings in the MSVC build. No functional changes intended. | Aaron Ballman | 2014-04-01 | 1 | -2/+2 |
| * | Try to fix MSan bootstrap bot: make ARM64Disassembler::getInstruction() alway... | Alexey Samsonov | 2014-03-31 | 1 | -2/+2 |
| * | [ARM64] Fix 'assert("...")' to be 'assert(0 && "...")'. Otherwise, it is | Chandler Carruth | 2014-03-29 | 1 | -1/+1 |
| * | ARM64: initial backend import | Tim Northover | 2014-03-29 | 1 | -0/+2142 |
