bcm5719-llvm - Project Ortega BCM5719 LLVM

	Commit message (Collapse)	Author	Age	Files	Lines
*	[C++11] Add 'override' keyword to virtual methods that override their base ↵	Craig Topper	2014-03-10	1	-7/+5
\| \| \| \| \| \|	class. llvm-svn: 203433
*	Don't cache the instruction and register info from the TargetMachine, because	Bill Wendling	2013-06-07	1	-3/+3
\| \| \| \| \| \|	the internals of TargetMachine could change. llvm-svn: 183488
*	Reorder includes to match coding standards. Fix an issue or two exposed by that.	Craig Topper	2012-03-17	1	-2/+1
\| \| \| \|	llvm-svn: 152978
*	Implement frame unwinding information emission for Thumb1. Not finished yet ↵	Anton Korobeynikov	2011-03-05	1	-1/+2
\| \| \| \| \| \|	because there is no way given the constpool index to examine the actual entry: the reason is clones inserted by constant island pass, which are not tracked at all! The only connection is done during asmprinting time via magic label names which is really gross and needs to be eventually fixed. llvm-svn: 127104
*	80-column cleanup of file header comments	Jim Grosbach	2009-11-07	1	-2/+3
\| \| \| \|	llvm-svn: 86408
*	Cleanup now that frame index scavenging via post-pass is working for ARM and ↵	Jim Grosbach	2009-10-28	1	-2/+0
\| \| \| \| \| \|	Thumb2. llvm-svn: 85406
*	- More refactoring. This gets rid of all of the getOpcode calls.	Evan Cheng	2009-07-28	1	-13/+0
\| \| \| \| \| \| \| \| \| \| \|	- This change also makes it possible to switch between ARM / Thumb on a per-function basis. - Fixed thumb2 routine which expand reg + arbitrary immediate. It was using using ARM so_imm logic. - Use movw and movt to do reg + imm when profitable. - Other code clean ups and minor optimizations. llvm-svn: 77300
*	Refactor. Get rid of a few more getOpcode() calls.	Evan Cheng	2009-07-26	1	-5/+13
\| \| \| \|	llvm-svn: 77164
*	Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index ↵	David Goodwin	2009-07-24	1	-6/+11
\| \| \| \| \| \|	elimination more exactly for Thumb-2 to get better code gen. llvm-svn: 76919
*	Let callers decide the sub-register index on the def operand of ↵	Evan Cheng	2009-07-16	1	-1/+1
\| \| \| \| \| \| \| \|	rematerialized instructions. Avoid remat'ing instructions whose def have sub-register indices for now. It's just really really hard to get all the cases right. llvm-svn: 75900
*	Use common code for both ARM and Thumb-2 instruction and register info.	David Goodwin	2009-07-08	1	-16/+0
\| \| \| \|	llvm-svn: 75067
*	Generalize opcode selection in ARMBaseRegisterInfo.	David Goodwin	2009-07-08	1	-1/+1
\| \| \| \|	llvm-svn: 75036
*	Push methods into base class in preparation for sharing.	David Goodwin	2009-07-08	1	-9/+8
\| \| \| \|	llvm-svn: 75020
*	Checkpoint refactoring of ThumbInstrInfo and ThumbRegisterInfo into ↵	David Goodwin	2009-07-02	1	-0/+60
	Thumb1InstrInfo, Thumb2InstrInfo, Thumb1RegisterInfo and Thumb2RegisterInfo. Move methods from ARMInstrInfo to ARMBaseInstrInfo to prepare for sharing with Thumb2. llvm-svn: 74731