| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | [ARM] Use helpers for adding pred / CC operands. NFC | Diana Picus | 2017-01-20 | 1 | -8/+10 |
| * | [ARM] CodeGen: Remove AddDefaultCC. NFC. | Diana Picus | 2017-01-13 | 1 | -1/+1 |
| * | [ARM] CodeGen: Remove AddDefaultPred. NFC. | Diana Picus | 2017-01-13 | 1 | -20/+31 |
| * | MachineFunction: Return reference for getFrameInfo(); NFC | Matthias Braun | 2016-07-28 | 1 | -2/+2 |
| * | Don't pass Reloc::Model to places that already have it. NFC. | Rafael Espindola | 2016-06-28 | 1 | -6/+6 |
| * | Pass DebugLoc and SDLoc by const ref. | Benjamin Kramer | 2016-06-12 | 1 | -7/+9 |
| * | [Thumb] A branch is not part of an IT block | James Molloy | 2016-06-09 | 1 | -1/+1 |
| * | ARM: Do not attempt to modify register class of physregs. | Matthias Braun | 2016-05-31 | 1 | -4/+9 |
| * | CodeGen: TII: Take MachineInstr& in predicate API, NFC | Duncan P. N. Exon Smith | 2016-02-23 | 1 | -6/+6 |
| * | PseudoSourceValue: Replace global manager with a manager in a machine function. | Alex Lorenz | 2015-08-11 | 1 | -10/+6 |
| * | MC: Modernize MCOperand API naming. NFC. | Jim Grosbach | 2015-05-13 | 1 | -3/+3 |
| * | [ARM] Do not generate invalid encoding for stack adjust, even if this is just | Quentin Colombet | 2015-04-30 | 1 | -2/+7 |
| * | Remove the need to cache the subtarget in the ARM TargetRegisterInfo | Eric Christopher | 2015-03-12 | 1 | -2/+1 |
| * | Fix handling of negative offsets for AddrModeT2_i8s4 in rewriteT2FrameIndex. | Bob Wilson | 2015-02-24 | 1 | -5/+2 |
| * | Fix incorrect immediate size for AddrModeT2_i8s4 in rewriteT2FrameIndex. | Bob Wilson | 2015-02-23 | 1 | -1/+1 |
| * | [ARM] In dynamic-no-pic mode, ARM's post-RA pseudo expansion was incorrectly | Akira Hatanaka | 2014-08-02 | 1 | -3/+3 |
| * | [stack protector] Fix a potential security bug in stack protector where the | Akira Hatanaka | 2014-07-25 | 1 | -0/+9 |
| * | Prune includes in ARM target. | Craig Topper | 2014-03-22 | 1 | -1/+0 |
| * | ARM: remove unnecessary state-tracking during frame lowering. | Tim Northover | 2013-11-04 | 1 | -0/+7 |
| * | Add hint disassembly syntax for 16-bit Thumb hint instructions. | Richard Barton | 2013-10-18 | 1 | -1/+2 |
| * | Fix PR 17372: Emitting PLD for stack address for ARM Thumb2 | Weiming Zhao | 2013-09-26 | 1 | -0/+7 |
| * | Reverting 190043 for now. | Tilmann Scheller | 2013-09-05 | 1 | -14/+2 |
| * | ARM: Add GPR register class excluding LR for use with the ADR instruction. | Tilmann Scheller | 2013-09-05 | 1 | -2/+14 |
| * | Don't cache the instruction and register info from the TargetMachine, because | Bill Wendling | 2013-06-07 | 1 | -1/+1 |
| * | Replace Count{Leading,Trailing}Zeros_{32,64} with count{Leading,Trailing}Zeros. | Michael J. Spencer | 2013-05-24 | 1 | -3/+3 |
| * | ARM: Use ldrd/strd to spill 64-bit pairs when available. | Tim Northover | 2013-04-21 | 1 | -20/+64 |
| * | Remove the explicit MachineInstrBuilder(MI) constructor. | Jakob Stoklund Olesen | 2012-12-19 | 1 | -1/+1 |
| * | Remove all references to TargetInstrInfoImpl. | Jakob Stoklund Olesen | 2012-11-28 | 1 | -2/+2 |
| * | Remove the TII::scheduleTwoAddrSource() hook. | Jakob Stoklund Olesen | 2012-08-13 | 1 | -42/+0 |
| * | Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change s... | Craig Topper | 2012-04-20 | 1 | -6/+6 |
| * | Prune some includes | Craig Topper | 2012-03-27 | 1 | -1/+0 |
| * | Remove unnecessary llvm:: qualifications | Craig Topper | 2012-03-27 | 1 | -5/+5 |
| * | Reorder includes to match coding standards. Fix an issue or two exposed by that. | Craig Topper | 2012-03-17 | 1 | -1/+0 |
| * | ARM implement TargetInstrInfo::getNoopForMachoTarget() | Jim Grosbach | 2012-02-28 | 1 | -0/+8 |
| * | Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430,... | Jia Liu | 2012-02-18 | 1 | -1/+1 |
| * | Handle regmask operands in ARMInstrInfo. | Jakob Stoklund Olesen | 2012-02-17 | 1 | -1/+1 |
| * | Make use of MachinePointerInfo::getFixedStack. This removes all mention | Jay Foad | 2011-11-15 | 1 | -5/+2 |
| * | Thumb1 ADD/SUB SP instructions are predicable in Thumb2 mode. | Jim Grosbach | 2011-08-24 | 1 | -3/+2 |
| * | Handle new register classes in Thumb2 mode. Should fix the ARM buildbots. | Owen Anderson | 2011-08-11 | 1 | -2/+4 |
| * | Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate A... | Evan Cheng | 2011-07-20 | 1 | -1/+1 |
| * | Refact ARM Thumb1 tMOVr instruction family. | Jim Grosbach | 2011-06-30 | 1 | -15/+4 |
| * | Thumb1 register to register MOV instruction is predicable. | Jim Grosbach | 2011-06-30 | 1 | -7/+7 |
| * | Kill dead code. | Jim Grosbach | 2011-06-30 | 1 | -1/+0 |
| * | Remove redundant Thumb2 ADD/SUB SP instruction definitions. | Jim Grosbach | 2011-06-29 | 1 | -6/+4 |
| * | Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.inc | Evan Cheng | 2011-06-28 | 1 | -1/+0 |
| * | - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and | Evan Cheng | 2011-06-28 | 1 | -1/+1 |
| * | Preliminary support for ARM frame save directives emission via MI flags. | Anton Korobeynikov | 2011-03-05 | 1 | -8/+11 |
| * | Guard against de-referencing MBB.end(). | Evan Cheng | 2011-02-22 | 1 | -1/+4 |
| * | Skipping over debugvalue instructions to determine whether the split spot is ... | Evan Cheng | 2011-02-21 | 1 | -0/+3 |
| * | Making use of VFP / NEON floating point multiply-accumulate / subtraction is | Evan Cheng | 2010-12-05 | 1 | -6/+0 |
