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path: root/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
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* Provide a legal pointer register class when targeting thumb1.Jakob Stoklund Olesen2011-03-311-0/+5
| | | | | | The LocalStackSlotAllocation pass was creating illegal registers. llvm-svn: 128687
* In Thumb1 mode the constant might be materialized via the load from ↵Anton Korobeynikov2011-03-051-3/+3
| | | | | | constpool. Emit unwinding information in case when this load from constpool is used to change the stack pointer in the prologue. llvm-svn: 127105
* Implement frame unwinding information emission for Thumb1. Not finished yet ↵Anton Korobeynikov2011-03-051-25/+35
| | | | | | because there is no way given the constpool index to examine the actual entry: the reason is clones inserted by constant island pass, which are not tracked at all! The only connection is done during asmprinting time via magic label names which is really gross and needs to be eventually fixed. llvm-svn: 127104
* Preliminary support for ARM frame save directives emission via MI flags.Anton Korobeynikov2011-03-051-13/+13
| | | | | | | This is just very first approximation how the stuff should be done (e.g. ARM-only for now). More to follow. llvm-svn: 127101
* When updating a tSpill/tRestore instruction to be a tSTRr/tLDRr, correctlyJim Grosbach2011-01-131-4/+7
| | | | | | | | | set up the source operands. The original instr has an immediate operand that should be replaced with the frame reg operand rather than just adding the reg operand. Previously, the instruction ended up with too many operands causing an assert() when adding the default predicate. rdar://8825456 llvm-svn: 123387
* Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs ↵Anton Korobeynikov2011-01-101-4/+4
| | | | | | and fixes here and there. llvm-svn: 123170
* If we're not using reg+reg offset we're using reg+imm, set the opcodeEric Christopher2010-12-211-2/+2
| | | | | | | | | to be the one we want to use. bugpoint reduced testcase is a little large, I'll see if I can simplify it down more. Fixes part of rdar://8782207 llvm-svn: 122307
* Add tSpill and tRestore to the opcodes to replace with tSTRi and tLDRiBill Wendling2010-12-161-0/+2
| | | | | | | | | respectively. It may be a bug that these opcodes are getting this far into machine code generation. llvm-svn: 121931
* Thumb1 had two patterns for the same load-from-constant-pool instruction.Jim Grosbach2010-12-151-1/+1
| | | | | | Canonicalize on tLDRpci and remove tLDRcp. llvm-svn: 121920
* If we're changing the frame register to a physical register other than SP, weBill Wendling2010-12-151-27/+37
| | | | | | need to use tLDRi and tSTRi instead of tLDRspi and tSTRspi respectively. llvm-svn: 121915
* The tLDR et al instructions were emitting either a reg/reg or reg/immBill Wendling2010-12-141-7/+4
| | | | | | | | | | | | | | | | instruction based on the t_addrmode_s# mode and what it returned. There is some obvious badness to this. In particular, it's hard to do MC-encoding when the instruction may change out from underneath you after the t_addrmode_s# variable is finally resolved. The solution is to revert a long-ago change that merged the reg/reg and reg/imm versions. There is the addition of several new addressing modes. They no longer have extraneous operands associated with them. I.e., if it's reg/reg we don't have to have a dummy zero immediate tacked on to the SDNode. There are some obvious cleanups here, which will happen shortly. llvm-svn: 121747
* Avoid release build warnings.Benjamin Kramer2010-11-191-2/+2
| | | | llvm-svn: 119804
* Move hasFP() and few related hooks to TargetFrameInfo.Anton Korobeynikov2010-11-181-15/+5
| | | | llvm-svn: 119740
* First step of huge frame-related refactoring: move emit{Prologue,Epilogue} ↵Anton Korobeynikov2010-11-151-203/+0
| | | | | | out of TargetRegisterInfo to TargetFrameInfo, which is definitely much better suitable place llvm-svn: 119097
* Revert r114340 (improvements in Darwin function prologue/epilogue), as it brokeJim Grosbach2010-11-021-11/+27
| | | | | | assumptions about stack layout. Specifically, LR must be saved next to FP. llvm-svn: 118026
* Add a pre-dispatch SjLj EH hook on the unwind edge for targets to do anyJim Grosbach2010-10-191-8/+7
| | | | | | | setup they require. Use this for ARM/Darwin to rematerialize the base pointer from the frame pointer when required. rdar://8564268 llvm-svn: 116879
* Simplify ARM callee-saved register handling by removing the distinctionJim Grosbach2010-09-201-27/+11
| | | | | | | | | | | | | | | | | | | between the high and low registers for prologue/epilogue code. This was a Darwin-only thing that wasn't providing a realistic benefit anymore. Combining the save areas simplifies the compiler code and results in better ARM/Thumb2 codegen. For example, previously we would generate code like: push {r4, r5, r6, r7, lr} add r7, sp, #12 stmdb sp!, {r8, r10, r11} With this change, we combine the register saves and generate: push {r4, r5, r6, r7, r8, r10, r11, lr} add r7, sp, #12 rdar://8445635 llvm-svn: 114340
* Re-apply r112883:Jim Grosbach2010-09-031-3/+13
| | | | | | | | | | | | | | "For ARM stack frames that utilize variable sized objects and have either large local stack areas or require dynamic stack realignment, allocate a base register via which to access the local frame. This allows efficient access to frame indices not accessible via the FP (either due to being out of range or due to dynamic realignment) or the SP (due to variable sized object allocation). In particular, this greatly improves efficiency of access to spill slots in Thumb functions which contain VLAs." r112986 fixed a latent bug exposed by the above. llvm-svn: 112989
* Revert "For ARM stack frames that utilize variable sized objects and have ↵Daniel Dunbar2010-09-031-13/+3
| | | | | | | | either", it is breaking oggenc with Clang for ARMv6. This reverts commit 8d6e29cfda270be483abf638850311670829ee65. llvm-svn: 112962
* For ARM stack frames that utilize variable sized objects and have eitherJim Grosbach2010-09-021-3/+13
| | | | | | | | | | | | | | | large local stack areas or require dynamic stack realignment, allocate a base register via which to access the local frame. This allows efficient access to frame indices not accessible via the FP (either due to being out of range or due to dynamic realignment) or the SP (due to variable sized object allocation). In particular, this greatly improves efficiency of access to spill slots in Thumb functions which contain VLAs. rdar://7352504 rdar://8374540 rdar://8355680 llvm-svn: 112883
* Simplify eliminateFrameIndex() interface back down now that PEI doesn't needJim Grosbach2010-08-261-13/+4
| | | | | | to try to re-use scavenged frame index reference registers. rdar://8277890 llvm-svn: 112241
* Add Thumb1 support for virtual frame indices.Jim Grosbach2010-08-191-112/+137
| | | | | | rdar://8277890 llvm-svn: 111533
* Re-apply r110655 with fixes. Epilogue must restore sp from fp if the ↵Evan Cheng2010-08-101-6/+5
| | | | | | | | function stack frame has a var-sized object. Also added a test case to check for the added benefit of this patch: it's optimizing away the unnecessary restore of sp from fp for some non-leaf functions. llvm-svn: 110707
* Revert r110655, "Fix ARM hasFP() semantics. It should return true whenever FPDaniel Dunbar2010-08-101-5/+6
| | | | | | register is", it breaks a couple test-suite tests. llvm-svn: 110701
* Fix ARM hasFP() semantics. It should return true whenever FP register isEvan Cheng2010-08-101-6/+5
| | | | | | | | | | reserved, not available for general allocation. This eliminates all the extra checks for Darwin. This change also fixes the use of FP to access frame indices in leaf functions and cleaned up some confusing code in epilogue emission. llvm-svn: 110655
* Constify some arguments.Eric Christopher2010-07-201-1/+1
| | | | llvm-svn: 108812
* Make getPhysicalRegisterRegClass non-virtual. Should be able to remove it soon.Rafael Espindola2010-07-111-15/+0
| | | | llvm-svn: 108094
* skip dbg_value instructionsJim Grosbach2010-06-291-0/+2
| | | | llvm-svn: 107154
* rdar://7937137 - dbg values not being handled in thumb1 version ofJim Grosbach2010-05-041-0/+7
| | | | | | eliminateFrameIndex(), leading to llvm_unreachable() assertion failure. llvm-svn: 102980
* ReuseFrameIndexVals is used in multiple files, so it can't be static.Dan Gohman2010-04-151-1/+4
| | | | llvm-svn: 101379
* Add const qualifiers to CodeGen's use of LLVM IR constructs.Dan Gohman2010-04-151-1/+1
| | | | llvm-svn: 101334
* use DebugLoc default ctor instead of DebugLoc::getUnknownLoc()Chris Lattner2010-04-021-3/+2
| | | | llvm-svn: 100214
* Change ARM ld/st multiple instructions to have variant instructions forBob Wilson2010-03-131-3/+2
| | | | | | | | | | | | | | | writebacks to the address register. This gets rid of the hack that the first register on the list was the magic writeback register operand. There was an implicit constraint that if that operand was not reg0 it had to match the base register operand. The post-RA scheduler's antidependency breaker did not understand that constraint and sometimes changed one without the other. This also fixes Radar 7495976 and should help the verifier work better for ARM code. There are now new ld/st instructions explicit writeback operands and explicit constraints that tie those registers together. llvm-svn: 98409
* comment why we use custom epilogue for t1 functions using vaargs.Jim Grosbach2010-03-101-0/+5
| | | | llvm-svn: 98182
* Clear up the last (famous last words) frame index value reuse issues for Thumb1.Jim Grosbach2010-03-101-1/+1
| | | | llvm-svn: 98109
* Change the Value argument to eliminateFrameIndex to a type-tagged value. ThisJim Grosbach2010-03-091-2/+3
| | | | | | | | | | is preparatory to having PEI's scavenged frame index value reuse logic properly distinguish types of frame values (e.g., whether the value is stack-pointer relative or frame-pointer relative). No functionality change. llvm-svn: 98086
* scavenged frame index value re-use gets confused when more than one baseJim Grosbach2010-03-091-0/+7
| | | | | | | | register is involved for thumb1. Work around this for the moment by only re-using SP-relative offsets. This is temporary 'til the code can distinguish multiple base registers. llvm-svn: 98071
* Thumb1 epilogue code generation needs to take into account that callee-savedJim Grosbach2010-03-061-4/+18
| | | | | | | registers may be restored via a pop instruction, not just a tRestore. This fixes nightly test 471.omnetep for Thumb1. llvm-svn: 97867
* handle very large call frames when require SPAdj != 0 for Thumb1Jim Grosbach2010-02-241-3/+3
| | | | llvm-svn: 97013
* Remove predicates when changing an add into an unpredicable mov.Jakob Stoklund Olesen2010-01-191-2/+6
| | | | | | | Since the mov is executed unconditionally, make sure that the add didn't have any predicate. llvm-svn: 93909
* improve portability to avoid conflicting with std::next in c++'0x.Chris Lattner2009-12-031-1/+1
| | | | | | Patch by Howard Hinnant! llvm-svn: 90365
* Use Unified Assembly Syntax for the ARM backend.Jim Grosbach2009-11-091-1/+1
| | | | llvm-svn: 86494
* 80-column cleanup of file header commentsJim Grosbach2009-11-071-2/+3
| | | | llvm-svn: 86408
* Cleanup now that frame index scavenging via post-pass is working for ARM and ↵Jim Grosbach2009-10-281-12/+0
| | | | | | Thumb2. llvm-svn: 85406
* Trim more includes.Evan Cheng2009-10-221-1/+0
| | | | llvm-svn: 84832
* Missing piece of the ARM frame index post-scavenging conditionalizationJim Grosbach2009-10-211-0/+12
| | | | llvm-svn: 84798
* Now that all ARM subtargets use frame index scavenging, the Thumb1 requires*Jim Grosbach2009-10-201-12/+0
| | | | | | functions are not needed. llvm-svn: 84587
* Enable allocation of R3 in Thumb1Jim Grosbach2009-10-191-1/+0
| | | | llvm-svn: 84563
* Adjust the scavenge register spilling to allow the target to choose anJim Grosbach2009-10-191-15/+32
| | | | | | | | | | appropriate restore location for the spill as well as perform the actual save and restore. The Thumb1 target uses this to make sure R12 is not clobbered while a spilled scavenger register is live there. llvm-svn: 84554
* Cleanup up unused R3LiveIn tracking.Jim Grosbach2009-10-081-9/+0
| | | | llvm-svn: 83522
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