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path: root/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
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* [ARM] Handle +t2dsp feature as an ArchExtKind in ARMTargetParser.defArtyom Skrobov2015-09-241-1/+1
| | | | | | | | | | | | | | | | | | Currently, the availability of DSP instructions (ACLE 6.4.7) is handled in a hand-rolled tricky condition block in tools/clang/lib/Basic/Targets.cpp, with a FIXME: attached. This patch changes the handling of +t2dsp to be in line with other architecture extensions. Following a revert of r248152 and new review comments, this patch also includes renaming FeatureDSPThumb2 -> FeatureDSP, hasThumb2DSP() -> hasDSP(), etc. The spelling of "t2dsp" is preserved, pending a further investigation of its possible external usage. Differential Revision: http://reviews.llvm.org/D12937 llvm-svn: 248519
* MC: Add target hook to control symbol quotingMatt Arsenault2015-06-091-5/+7
| | | | llvm-svn: 239370
* Revert r238473, "Thumb2: Modify codegen for memcpy intrinsic to prefer LDM/STM."Peter Collingbourne2015-06-051-14/+3
| | | | | | | as it caused miscompilations and assertion failures (PR23768, http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20150601/280380.html). llvm-svn: 239169
* MC: Clean up MCExpr naming. NFC.Jim Grosbach2015-05-301-1/+1
| | | | llvm-svn: 238634
* Thumb2: Modify codegen for memcpy intrinsic to prefer LDM/STM.Peter Collingbourne2015-05-281-3/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | We were previously codegen'ing these as regular load/store operations and hoping that the register allocator would allocate registers in ascending order so that we could apply an LDM/STM combine after register allocation. According to the commit that first introduced this code (r37179), we planned to teach the register allocator to allocate the registers in ascending order. This never got implemented, and up to now we've been stuck with very poor codegen. A much simpler approach for achiveing better codegen is to create LDM/STM instructions with identical sets of virtual registers, let the register allocator pick arbitrary registers and order register lists when printing an MCInst. This approach also avoids the need to repeatedly calculate offsets which ultimately ought to be eliminated pre-RA in order to decrease register pressure. This is implemented by lowering the memcpy intrinsic to a series of SD-only MCOPY pseudo-instructions which performs a memory copy using a given number of registers. During SD->MI lowering, we lower MCOPY to LDM/STM. This is a little unusual, but it avoids the need to encode register lists in the SD, and we can take advantage of SD use lists to decide whether to use the _UPD variant of the instructions. Fixes PR9199. Differential Revision: http://reviews.llvm.org/D9508 llvm-svn: 238473
* Use std::bitset for SubtargetFeatures.Michael Kuperstein2015-05-261-7/+7
| | | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. The first several times this was committed (e.g. r229831, r233055), it caused several buildbot failures. Apparently the reason for most failures was both clang and gcc's inability to deal with large numbers (> 10K) of bitset constructor calls in tablegen-generated initializers of instruction info tables. This should now be fixed. llvm-svn: 238192
* MC: Modernize MCOperand API naming. NFC.Jim Grosbach2015-05-131-1/+1
| | | | | | MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
* Reverting r237234, "Use std::bitset for SubtargetFeatures"Michael Kuperstein2015-05-131-7/+7
| | | | | | | The buildbots are still not satisfied. MIPS and ARM are failing (even though at least MIPS was expected to pass). llvm-svn: 237245
* Use std::bitset for SubtargetFeaturesMichael Kuperstein2015-05-131-7/+7
| | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. The first two times this was committed (r229831, r233055), it caused several buildbot failures. At least some of the ARM and MIPS ones were due to gcc/binutils issues, and should now be fixed. llvm-svn: 237234
* [ARM] Simplify code. NFC.Benjamin Kramer2015-04-251-15/+2
| | | | llvm-svn: 235803
* Remove unused MCSubtargetInfo argument from the ARM MCInstPrinter ctors.Eric Christopher2015-03-301-2/+1
| | | | llvm-svn: 233609
* [ARM] Enable changing instprinter's behavior based on the per-functionAkira Hatanaka2015-03-271-67/+133
| | | | | | subtarget. llvm-svn: 233451
* clang-format ARMInstPrinter.{h,cpp} before I make changes to these files.Akira Hatanaka2015-03-271-259/+275
| | | | llvm-svn: 233448
* [MCInstPrinter] Enable MCInstPrinter to change its behavior based on theAkira Hatanaka2015-03-271-1/+1
| | | | | | | | | | | | | | | | | | | | per-function subtarget. Currently, code-gen passes the default or generic subtarget to the constructors of MCInstPrinter subclasses (see LLVMTargetMachine::addPassesToEmitFile), which enables some targets (AArch64, ARM, and X86) to change their instprinter's behavior based on the subtarget feature bits. Since the backend can now use different subtargets for each function, instprinter has to be changed to use the per-function subtarget rather than the default subtarget. This patch takes the first step towards enabling instprinter to change its behavior based on the per-function subtarget. It adds a bit "PassSubtarget" to AsmWriter which tells table-gen to pass a reference to MCSubtargetInfo to the various print methods table-gen auto-generates. I will follow up with changes to instprinters of AArch64, ARM, and X86. llvm-svn: 233411
* Fix remaining MSVC warningAndrew Kaylor2015-03-251-2/+2
| | | | llvm-svn: 233220
* Revert "Use std::bitset for SubtargetFeatures"Michael Kuperstein2015-03-241-7/+7
| | | | | | | | This reverts commit r233055. It still causes buildbot failures (gcc running out of memory on several platforms, and a self-host failure on arm), although less than the previous time. llvm-svn: 233068
* Use std::bitset for SubtargetFeaturesMichael Kuperstein2015-03-241-7/+7
| | | | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. The first time this was committed (r229831), it caused several buildbot failures. At least some of the ARM ones were due to gcc/binutils issues, and should now be fixed. Differential Revision: http://reviews.llvm.org/D8542 llvm-svn: 233055
* Reverting r229831 due to multiple ARM/PPC/MIPS build-bot failures.Michael Kuperstein2015-02-191-7/+7
| | | | llvm-svn: 229841
* Use std::bitset for SubtargetFeaturesMichael Kuperstein2015-02-191-7/+7
| | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. Differential Revision: http://reviews.llvm.org/D7065 llvm-svn: 229831
* Add support for ARM modified-immediate assembly syntax.Asiri Rathnayake2014-12-021-0/+46
| | | | | | | | | | | | | | | | | | | | Certain ARM instructions accept 32-bit immediate operands encoded as a 8-bit integer value (0-255) and a 4-bit rotation (0-30, even). Current ARM assembly syntax support in LLVM allows the decoded (32-bit) immediate to be specified as a single immediate operand for such instructions: mov r0, #4278190080 The ARMARM defines an extended assembly syntax allowing the encoding to be made more explicit, as in: mov r0, #255, #8 ; (same 32-bit value as above) The behaviour of the two instructions can be different w.r.t flags, which is documented under "Modified immediate constants" in ARMARM. This patch enables support for this extended syntax at the MC layer. llvm-svn: 223113
* Add Thumb HVC and ERET virtualisation extension instructions.Charlie Turner2014-12-011-0/+15
| | | | | | | Patch by Matthew Wahab. Change-Id: I131f71c1150d5fa797066a18e09d526c19bf9016 llvm-svn: 222990
* Add ARM ERET and HVC virtualisation extension instructions.Charlie Turner2014-12-011-1/+3
| | | | | | | Patch by Matthew Wahab. Change-Id: Iad75f078fbaa4ecc7d7a4820ad9b3930679cbbbb llvm-svn: 222989
* ARMInstPrinter.cpp: Suppress a warning for -Asserts. [-Wunused-variable]NAKAMURA Takumi2014-10-061-3/+2
| | | | llvm-svn: 219172
* ARM: silence unused variable warningTim Northover2014-10-061-2/+2
| | | | llvm-svn: 219128
* ARM: remove dead InstPrinting codeTim Northover2014-10-061-28/+1
| | | | | | | This instruction form is handled by different AsmOperands now, so the code is completely dead (and wrong anyway). llvm-svn: 219127
* Thumb2 M-class MSR instruction support changesRenato Golin2014-09-011-41/+45
| | | | | | | | | | | | This patch implements a few changes related to the Thumb2 M-class MSR instruction: * better handling of unpredictable encodings, * recognition of the _g and _nzcvqg variants by the asm parser only if the DSP extension is available, preferred output of MSR APSR moves with the _<bits> suffix for v7-M. Patch by Petr Pavlu. llvm-svn: 216874
* ARM: implement MRS/MSR (banked reg) system instructions.Tim Northover2014-08-151-0/+36
| | | | | | | | | | These are system-only instructions for CPUs with virtualization extensions, allowing a hypervisor easy access to all of the various different AArch32 registers. rdar://problem/17861345 llvm-svn: 215700
* ARM: honor hex immediate formatting for ldr/str i12 offsets.Jim Grosbach2014-06-111-2/+2
| | | | | | | | | | | | | | | | | Previously we would always print the offset as decimal, regardless of the formatting requested. Now we use the formatImm() helper so the value is printed as the client (LLDB in the motivating example) requested. Before: ldr.w r8, [sp, #180] @ always After: ldr.w r8, [sp, #0xb4] @ when printing hex immediates ldr.w r8, [sp, #0180] @ when printing decimal immediates rdar://17237103 llvm-svn: 210701
* [Modules] Fix potential ODR violations by sinking the DEBUG_TYPEChandler Carruth2014-04-221-1/+2
| | | | | | | definition below all of the header #include lines, lib/Target/... edition. llvm-svn: 206842
* ARM IAS: properly handle expression operandsSaleem Abdulrasool2014-01-081-10/+23
| | | | | | | Operands which involved label arithemetic would previously fail to parse. This corrects that by adding the additional case for the shift operand validation. llvm-svn: 198735
* Pure refactoring change.Richard Barton2013-10-181-73/+86
| | | | | | Patch by Artyom Skrobov. llvm-svn: 192977
* Add hint disassembly syntax for 16-bit Thumb hint instructions.Richard Barton2013-10-181-1/+1
| | | | | | Patch by Artyom Skrobov llvm-svn: 192972
* [ARM] Introduce the 'sevl' instruction in ARMv8.Joey Gouly2013-10-011-0/+5
| | | | | | | This also removes the restriction on the immediate field of the 'hint' instruction. llvm-svn: 191744
* [ARMv8] Implement the new DMB/DSB operands.Joey Gouly2013-09-051-1/+1
| | | | | | | This removes the custom ISD Node: MEMBARRIER and replaces it with an intrinsic. llvm-svn: 190055
* [ARMv8] Add MC support for the new load/store acquire/release instructions.Joey Gouly2013-08-271-2/+3
| | | | llvm-svn: 189388
* This corrects the implementation of Thumb ADR instruction. There are three ↵Mihai Popa2013-07-031-1/+2
| | | | | | | | | | issues: 1. it should accept only 4-byte aligned addresses 2. the maximum offset should be 1020 3. it should be encoded with the offset scaled by two bits llvm-svn: 185528
* ARM: operands should be explicit when disassembledAmaury de la Vieuville2013-06-261-8/+3
| | | | llvm-svn: 184943
* ARM: fix thumb1 nop decodingAmaury de la Vieuville2013-06-241-9/+0
| | | | | | | In thumb1, NOP is a pseudo-instruction equivalent to mov r8, r8. However the disassembler should not use this alias. llvm-svn: 184703
* ARM: add operands pre-writeback variants when neededAmaury de la Vieuville2013-06-181-22/+28
| | | | llvm-svn: 184181
* ARM: fix thumb literal loads decodingAmaury de la Vieuville2013-06-181-7/+21
| | | | | | | | This fixes two previous issues: - Negative offsets were not correctly disassembled - The decoded opcodes were not the right one llvm-svn: 184180
* ARM: fix t2am_imm8_offset operand printing for imm=#-0Amaury de la Vieuville2013-06-131-1/+3
| | | | llvm-svn: 183913
* ARM: ISB cannot be passed the same options as DMBAmaury de la Vieuville2013-06-101-0/+6
| | | | | | ISB should only accepts full system sync, other options are reserved llvm-svn: 183656
* Replace Count{Leading,Trailing}Zeros_{32,64} with count{Leading,Trailing}Zeros.Michael J. Spencer2013-05-241-3/+3
| | | | llvm-svn: 182680
* ARM: Correct printing of pre-indexed operands.Quentin Colombet2013-04-121-7/+11
| | | | | | | | | | | | | According to the ARM reference manual, constant offsets are mandatory for pre-indexed addressing modes. The MC disassembler was not obeying this when the offset is 0. It was producing instructions like: str r0, [r1]!. Correct syntax is: str r0, [r1, #0]!. This change modifies the dumping of operands so that the offset is always printed, regardless of its value, when pre-indexed addressing mode is used. Patch by Mihail Popa <Mihail.Popa@arm.com> llvm-svn: 179398
* Make ARMAsmPrinter generate the correct alignment specifier syntax in ↵Kristof Beyls2013-02-221-2/+1
| | | | | | | | | instructions. The Printer will now print instructions with the correct alignment specifier syntax, like vld1.8 {d16}, [r0:64] llvm-svn: 175884
* Added a option to the disassembler to print immediates as hex.Kevin Enderby2012-12-051-7/+7
| | | | | | | | | | | | | | | | | | | | This is for the lldb team so most of but not all of the values are to be printed as hex with this option. Some small values like the scale in an X86 address were requested to printed in decimal without the leading 0x. There may be some tweaks need to places that may still be in decimal that they want in hex. Specially for arm. I made my best guess. Any tweaks from here should be simple. I also did the best I know now with help from the C++ gurus creating the cleanest formatImm() utility function and containing the changes. But if someone has a better idea to make something cleaner I'm all ears and game for changing the implementation. rdar://8109283 llvm-svn: 169393
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-2/+2
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
* Remove hard coded registers in ARM ldrexd and strexd instructionsWeiming Zhao2012-11-161-0/+38
| | | | | | | | | This patch replaces the hard coded GPR pair [R0, R1] of Intrinsic:arm_ldrexd and [R2, R3] of Intrinsic:arm_strexd with even/odd GPRPair reg class. Similar to the lowering of atomic_64 operation. llvm-svn: 168207
* ARM: Better disassembly for pc-relative LDR.Jim Grosbach2012-10-301-2/+2
| | | | | | | | | When the operand is a plain immediate rather than a label, print it as [pc, #imm] like we do for the Thumb2 wide encoding variant. rdar://12154503 llvm-svn: 166991
* Make branch heavy code for generating marked up disassembly simplerKevin Enderby2012-10-231-304/+142
| | | | | | | and easier to read by adding a couple helper functions. Suggestion by Chandler Carruth and seconded by Meador Inge! llvm-svn: 166515
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