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authorJoey Gouly <joey.gouly@arm.com>2013-08-27 17:38:16 +0000
committerJoey Gouly <joey.gouly@arm.com>2013-08-27 17:38:16 +0000
commite6d165ccb4fdecdfa5f8815b33e4074348f32a03 (patch)
tree097342e6e172d5a1d9c6ae84f8b240e7b6499386 /llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
parent35c6b614ea6082727bb1fd529449965e64e5f87a (diff)
downloadbcm5719-llvm-e6d165ccb4fdecdfa5f8815b33e4074348f32a03.tar.gz
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[ARMv8] Add MC support for the new load/store acquire/release instructions.
llvm-svn: 189388
Diffstat (limited to 'llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp')
-rw-r--r--llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp5
1 files changed, 3 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp b/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
index 97da232cf08..8b99c17da58 100644
--- a/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
+++ b/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
@@ -249,9 +249,10 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
// GPRs. However, when decoding them, the two GRPs cannot be automatically
// expressed as a GPRPair, so we have to manually merge them.
// FIXME: We would really like to be able to tablegen'erate this.
- if (Opcode == ARM::LDREXD || Opcode == ARM::STREXD) {
+ if (Opcode == ARM::LDREXD || Opcode == ARM::STREXD ||
+ Opcode == ARM::LDAEXD || Opcode == ARM::STLEXD) {
const MCRegisterClass& MRC = MRI.getRegClass(ARM::GPRRegClassID);
- bool isStore = Opcode == ARM::STREXD;
+ bool isStore = Opcode == ARM::STREXD || Opcode == ARM::STLEXD;
unsigned Reg = MI->getOperand(isStore ? 1 : 0).getReg();
if (MRC.contains(Reg)) {
MCInst NewMI;
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