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| author | Michael Kuperstein <michael.m.kuperstein@intel.com> | 2015-02-19 11:38:11 +0000 |
|---|---|---|
| committer | Michael Kuperstein <michael.m.kuperstein@intel.com> | 2015-02-19 11:38:11 +0000 |
| commit | efd7a96d2e8ff886fb2a1bc755dd6355b2bb5f17 (patch) | |
| tree | c0afe1a7e7975789a575b441ac8e4e988da8f49c /llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp | |
| parent | 9570ff94f7f19af86a5f0cf3ea2992173980b3d8 (diff) | |
| download | bcm5719-llvm-efd7a96d2e8ff886fb2a1bc755dd6355b2bb5f17.tar.gz bcm5719-llvm-efd7a96d2e8ff886fb2a1bc755dd6355b2bb5f17.zip | |
Reverting r229831 due to multiple ARM/PPC/MIPS build-bot failures.
llvm-svn: 229841
Diffstat (limited to 'llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp b/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp index 41287df8276..16eea335261 100644 --- a/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp +++ b/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp @@ -90,7 +90,7 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O, case 3: O << "\twfi"; break; case 4: O << "\tsev"; break; case 5: - if (getAvailableFeatures()[ARM::HasV8Ops]) { + if ((getAvailableFeatures() & ARM::HasV8Ops)) { O << "\tsevl"; break; } // Fallthrough for non-v8 @@ -299,7 +299,7 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O, if (MI->getNumOperands() == 3 && MI->getOperand(0).isImm() && MI->getOperand(0).getImm() == 0 && - getAvailableFeatures()[ARM::FeatureVirtualization]) { + (getAvailableFeatures() & ARM::FeatureVirtualization)) { O << "\teret"; printPredicateOperand(MI, 1, O); printAnnotation(O, Annot); @@ -698,7 +698,7 @@ void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI, void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum, raw_ostream &O) { unsigned val = MI->getOperand(OpNum).getImm(); - O << ARM_MB::MemBOptToString(val, getAvailableFeatures()[ARM::HasV8Ops]); + O << ARM_MB::MemBOptToString(val, (getAvailableFeatures() & ARM::HasV8Ops)); } void ARMInstPrinter::printInstSyncBOption(const MCInst *MI, unsigned OpNum, @@ -796,14 +796,14 @@ void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum, const MCOperand &Op = MI->getOperand(OpNum); unsigned SpecRegRBit = Op.getImm() >> 4; unsigned Mask = Op.getImm() & 0xf; - const FeatureBitset &FeatureBits = getAvailableFeatures(); + uint64_t FeatureBits = getAvailableFeatures(); - if (FeatureBits[ARM::FeatureMClass]) { + if (FeatureBits & ARM::FeatureMClass) { unsigned SYSm = Op.getImm(); unsigned Opcode = MI->getOpcode(); // For writes, handle extended mask bits if the DSP extension is present. - if (Opcode == ARM::t2MSR_M && FeatureBits[ARM::FeatureDSPThumb2]) { + if (Opcode == ARM::t2MSR_M && (FeatureBits & ARM::FeatureDSPThumb2)) { switch (SYSm) { case 0x400: O << "apsr_g"; return; case 0xc00: O << "apsr_nzcvqg"; return; @@ -819,7 +819,7 @@ void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum, // Handle the basic 8-bit mask. SYSm &= 0xff; - if (Opcode == ARM::t2MSR_M && FeatureBits [ARM::HasV7Ops]) { + if (Opcode == ARM::t2MSR_M && (FeatureBits & ARM::HasV7Ops)) { // ARMv7-M deprecates using MSR APSR without a _<bits> qualifier as an // alias for MSR APSR_nzcvq. switch (SYSm) { |
