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path: root/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
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* Fix #13035, a bug around Thumb instruction LDRD/STRD with negative #0 offset ↵Jiangning Liu2012-08-021-12/+19
| | | | | | index issue. llvm-svn: 161162
* Fix #13241, a bug around shift immediate operand for ARM instruction ADR.Jiangning Liu2012-08-021-0/+19
| | | | llvm-svn: 161159
* ARM: Define generic HINT instruction.Jim Grosbach2012-06-181-0/+21
| | | | | | | | | | | The NOP, WFE, WFI, SEV and YIELD instructions are all hints w/ a different immediate value in bits [7,0]. Define a generic HINT instruction and refactor NOP, WFI, WFI, SEV and YIELD to be assembly aliases of that. rdar://11600518 llvm-svn: 158674
* Fix the encoding of the armv7m (MClass) for MSR registers other than aspr,Kevin Enderby2012-06-151-10/+20
| | | | | | iaspr, espr and xpsr which also needed to have 0b10 in their mask encoding bits. llvm-svn: 158560
* Fix the encoding of the armv7m (MClass) for MSR APSR writes which was missingKevin Enderby2012-05-171-5/+23
| | | | | | | | | | the 0b10 mask encoding bits. Make MSR APSR writes without a _<bits> qualifier an alias for MSR APSR_nzcvq even though ARM as deprecated it use. Also add support for suffixes (_nzcvq, _g, _nzcvqg) for APSR versions. Some FIXMEs in the code for better error checking when versions shouldn't be used. rdar://11457025 llvm-svn: 157019
* Fixed the LLVM ARM v7 assembler and instruction printer for 8-bit immediate ↵Silviu Baranga2012-05-111-2/+6
| | | | | | offset addressing. The assembler and instruction printer were not properly handeling the #-0 immediate. llvm-svn: 156608
* Refactor IT handling not to store the bottom bit of the condition code in ↵Richard Barton2012-04-271-1/+2
| | | | | | the mask operand in the MCInst. llvm-svn: 155700
* For ARM disassembly only print 32 unsigned bits for the address of branchKevin Enderby2012-04-131-2/+2
| | | | | | | targets so if the branch target has the high bit set it does not get printed as: beq 0xffffffff8008c404 llvm-svn: 154685
* Move getOpcodeName from the various target InstPrinters into the superclass ↵Benjamin Kramer2012-04-021-4/+0
| | | | | | | | MCInstPrinter. All implementations used the same code. llvm-svn: 153866
* Remove getInstructionName from MCInstPrinter implementations in favor of ↵Craig Topper2012-04-021-2/+2
| | | | | | using the instruction name table from MCInstrInfo. Reduces static data in the InstPrinter implementations. llvm-svn: 153863
* Make MCInstrInfo available to the MCInstPrinter. This will be used to remove ↵Craig Topper2012-04-021-1/+2
| | | | | | getInstructionName and the static data it contains since the same tables are already in MCInstrInfo. llvm-svn: 153860
* ARM more NEON VLD/VST composite physical register refactoring.Jim Grosbach2012-03-061-5/+4
| | | | | | Register pair, all lanes subscripting. llvm-svn: 152157
* ARM refactor more NEON VLD/VST instructions to use composite physregsJim Grosbach2012-03-061-18/+8
| | | | | | | Register pair VLD1/VLD2 all-lanes instructions. Kill off more of the pseudos as a result. llvm-svn: 152150
* Tidy up. Kill some dead code.Jim Grosbach2012-03-061-9/+0
| | | | llvm-svn: 152131
* ARM Refactor VLD/VST spaced pair instructions.Jim Grosbach2012-03-051-0/+9
| | | | | | Use the new composite physical registers. llvm-svn: 152063
* ARM refactor away a bunch of VLD/VST pseudo instructions.Jim Grosbach2012-03-051-0/+9
| | | | | | | | | With the new composite physical registers to represent arbitrary pairs of DPR registers, we don't need the pseudo-registers anymore. Get rid of a bunch of them that use DPR register pairs and just use the real instructions directly instead. llvm-svn: 152045
* Make MCRegisterInfo available to the the MCInstPrinter.Jim Grosbach2012-03-051-1/+2
| | | | | | | Used to allow context sensitive printing of super-register or sub-register references. llvm-svn: 152043
* Change ARMInstPrinter::printPredicateOperand() so it will not abort if itKevin Enderby2012-03-011-1/+4
| | | | | | runs into the undefined 15 condition code value. llvm-svn: 151844
* Remove dead code. Improve llvm_unreachable text. Simplify some control flow.Ahmed Charles2012-02-191-1/+0
| | | | llvm-svn: 150918
* Convert assert(0) to llvm_unreachableCraig Topper2012-02-071-2/+2
| | | | llvm-svn: 149961
* NEON VLD4(all lanes) assembly parsing and encoding.Jim Grosbach2012-01-251-1/+25
| | | | llvm-svn: 148884
* NEON VLD3(all lanes) assembly parsing and encoding.Jim Grosbach2012-01-241-0/+22
| | | | llvm-svn: 148882
* NEON VLD4(multiple 4 element structures) assembly parsing.Jim Grosbach2012-01-241-0/+12
| | | | llvm-svn: 148762
* NEON VLD3(multiple 3-element structures) assembly parsing.Jim Grosbach2012-01-231-0/+10
| | | | llvm-svn: 148745
* ARM VFP assembly parsing and encoding for VCVT(float <--> fixed point).Jim Grosbach2011-12-221-0/+10
| | | | | | rdar://10558523 llvm-svn: 147189
* ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback.Jim Grosbach2011-12-211-0/+10
| | | | llvm-svn: 147025
* ARM assembly parsing and encoding support for LDRD(label).Jim Grosbach2011-12-191-0/+11
| | | | | | rdar://9932658 llvm-svn: 146921
* ARM NEON VST2 assembly parsing and encoding.Jim Grosbach2011-12-141-0/+10
| | | | | | | | Work in progress. Parsing for non-writeback, single spaced register lists works now. The rest have the representations better factored, but still need more to be able to parse properly. llvm-svn: 146579
* ARM parsing for VLD1 two register all lanes, no writeback.Jim Grosbach2011-11-301-0/+9
| | | | llvm-svn: 145504
* ARM parsing aliases for VLD1 single register all lanes.Jim Grosbach2011-11-301-0/+7
| | | | llvm-svn: 145464
* Simplify some uses of utohexstr.Benjamin Kramer2011-11-071-2/+2
| | | | | | As a side effect hex is printed lowercase instead of uppercase now. llvm-svn: 144013
* Fix the issue that r143552 was trying to address the _right_ way. ↵Owen Anderson2011-11-021-2/+6
| | | | | | One-register lists are legal on LDM/STM instructions, but we should not print the PUSH/POP aliases when they appear. This fixes round tripping on this instruction. llvm-svn: 143557
* Assembly parsing for 4-register variant of VLD1.Jim Grosbach2011-10-211-0/+11
| | | | llvm-svn: 142682
* Assembly parsing for 3-register variant of VLD1.Jim Grosbach2011-10-211-0/+10
| | | | llvm-svn: 142675
* ARM VLD parsing and encoding.Jim Grosbach2011-10-211-0/+9
| | | | | | | | | | | | Next step in the ongoing saga of NEON load/store assmebly parsing. Handle VLD1 instructions that take a two-register register list. Adjust the instruction definitions to only have the single encoded register as an operand. The super-register from the pseudo is kept as an implicit def, so passes which come after pseudo-expansion still know that the instruction defines the other subregs. llvm-svn: 142670
* whitespace.Jim Grosbach2011-10-211-1/+1
| | | | llvm-svn: 142657
* ARM VTBL (one register) assembly parsing and encoding.Jim Grosbach2011-10-181-0/+5
| | | | llvm-svn: 142441
* ARM parsing and encoding for the <option> form of LDC/STC instructions.Jim Grosbach2011-10-121-0/+5
| | | | llvm-svn: 141786
* 80 columns.Jim Grosbach2011-10-121-2/+1
| | | | llvm-svn: 141781
* Tidy up. Formatting.Jim Grosbach2011-10-121-2/+2
| | | | llvm-svn: 141780
* ARM NEON assembly parsing and encoding for VDUP(scalar).Jim Grosbach2011-10-071-0/+5
| | | | llvm-svn: 141446
* Support a valid, but not very useful, encoding of CPSIE where none of the ↵Owen Anderson2011-10-051-0/+3
| | | | | | AIF bits are set. llvm-svn: 141190
* Adding back support for printing operands symbolically to ARM's new disassemblerKevin Enderby2011-10-041-1/+12
| | | | | | | | | | | | | | | | | | | using llvm's public 'C' disassembler API now including annotations. Hooked this up to Darwin's otool(1) so it can again print things like branch targets for example this: blx _puts instead of this: blx #-36 and includes support for annotations for branches to symbol stubs like: bl 0x40 @ symbol stub for: _puts and annotations for pc relative loads like this: ldr r3, #8 @ literal pool for: Hello, world! Also again can print the expression encoded in the Mach-O relocation entries for things like this: movt r0, :upper16:((_foo-_bar)+1234) llvm-svn: 141129
* ARM fix encoding of VMOV.f32 and VMOV.f64 immediates.Jim Grosbach2011-09-301-32/+3
| | | | | | | | | | | Encode the immediate into its 8-bit form as part of isel rather than later, which simplifies things for mapping the encoding bits, allows the removal of the custom disassembler decoding hook, makes the operand printer trivial, and prepares things more cleanly for handling these in the asm parser. rdar://10211428 llvm-svn: 140834
* Check in a patch that has already been code reviewed by Owen that I'd ↵James Molloy2011-09-281-0/+20
| | | | | | | | | | | | forgotten to commit. Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format. Add decoder and disassembler tests. Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT. llvm-svn: 140696
* Post-index loads/stores in still need to print the post-indexed immediate, ↵Owen Anderson2011-09-231-3/+3
| | | | | | even if it's zero, to distinguish them from non-post-indexed instructions. llvm-svn: 140420
* Turns out that Thumb2 ADR doesn't need special printing like LDR does. Fix ↵Owen Anderson2011-09-211-12/+0
| | | | | | other test failures I caused. llvm-svn: 140284
* Print out immediate offset versions of PC-relative load/store instructions ↵Owen Anderson2011-09-211-0/+23
| | | | | | as [pc, #123] rather than simply #123. llvm-svn: 140283
* These do not need to be conditional on the presence of CommentStream, as ↵Owen Anderson2011-09-211-12/+12
| | | | | | they have a fallback path now. llvm-svn: 140267
* In the disassembler C API, be careful not to confuse the comment streamer ↵Owen Anderson2011-09-211-12/+12
| | | | | | that the disassembler outputs annotations on with the streamer that the InstPrinter will print them on. llvm-svn: 140217
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