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| author | Jim Grosbach <grosbach@apple.com> | 2012-03-06 22:01:44 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2012-03-06 22:01:44 +0000 |
| commit | 13a292cc74422c16f6eee1cddad9e523318eb0d3 (patch) | |
| tree | e0eda22948e3bab241dfcf4bdf353730b326cd48 /llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp | |
| parent | 75383bf34dc8069f260e8639783c481224b90dc6 (diff) | |
| download | bcm5719-llvm-13a292cc74422c16f6eee1cddad9e523318eb0d3.tar.gz bcm5719-llvm-13a292cc74422c16f6eee1cddad9e523318eb0d3.zip | |
ARM refactor more NEON VLD/VST instructions to use composite physregs
Register pair VLD1/VLD2 all-lanes instructions. Kill off more of the
pseudos as a result.
llvm-svn: 152150
Diffstat (limited to 'llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp | 26 |
1 files changed, 8 insertions, 18 deletions
diff --git a/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp b/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp index 590cf0e720b..8754053d62a 100644 --- a/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp +++ b/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp @@ -1025,7 +1025,7 @@ void ARMInstPrinter::printVectorListOne(const MCInst *MI, unsigned OpNum, O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "}"; } -void ARMInstPrinter::printVectorListDPair(const MCInst *MI, unsigned OpNum, +void ARMInstPrinter::printVectorListTwo(const MCInst *MI, unsigned OpNum, raw_ostream &O) { unsigned Reg = MI->getOperand(OpNum).getReg(); unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); @@ -1033,9 +1033,9 @@ void ARMInstPrinter::printVectorListDPair(const MCInst *MI, unsigned OpNum, O << "{" << getRegisterName(Reg0) << ", " << getRegisterName(Reg1) << "}"; } -void ARMInstPrinter::printVectorListDPairSpaced(const MCInst *MI, - unsigned OpNum, - raw_ostream &O) { +void ARMInstPrinter::printVectorListTwoSpaced(const MCInst *MI, + unsigned OpNum, + raw_ostream &O) { unsigned Reg = MI->getOperand(OpNum).getReg(); unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2); @@ -1072,11 +1072,10 @@ void ARMInstPrinter::printVectorListOneAllLanes(const MCInst *MI, void ARMInstPrinter::printVectorListTwoAllLanes(const MCInst *MI, unsigned OpNum, raw_ostream &O) { - // Normally, it's not safe to use register enum values directly with - // addition to get the next register, but for VFP registers, the - // sort order is guaranteed because they're all of the form D<n>. - O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[], " - << getRegisterName(MI->getOperand(OpNum).getReg() + 1) << "[]}"; + unsigned Reg = MI->getOperand(OpNum).getReg(); + unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); + unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1); + O << "{" << getRegisterName(Reg0) << "[], " << getRegisterName(Reg1) << "[]}"; } void ARMInstPrinter::printVectorListThreeAllLanes(const MCInst *MI, @@ -1102,15 +1101,6 @@ void ARMInstPrinter::printVectorListFourAllLanes(const MCInst *MI, << getRegisterName(MI->getOperand(OpNum).getReg() + 3) << "[]}"; } -void ARMInstPrinter::printVectorListTwoSpaced(const MCInst *MI, unsigned OpNum, - raw_ostream &O) { - // Normally, it's not safe to use register enum values directly with - // addition to get the next register, but for VFP registers, the - // sort order is guaranteed because they're all of the form D<n>. - O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << ", " - << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "}"; -} - void ARMInstPrinter::printVectorListTwoSpacedAllLanes(const MCInst *MI, unsigned OpNum, raw_ostream &O) { |
