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* Fix treatment of ARM unallocated hint instructions.Quentin Colombet2013-04-171-0/+11
| | | | | | | | | | | | | | | The reference manual defines only 5 permitted values for the immediate field of the "hint" instruction: 1. nop (imm == 0) 2. yield (imm == 1) 3. wfe (imm == 2) 4. wfi (imm == 3) 5. sev (imm == 4) Therefore, restrict the permitted values for the "hint" instruction to 0 through 4. Patch by Mihail Popa <Mihail.Popa@arm.com> llvm-svn: 179707
* Fix issue with disassembler decoding CBZ/CBNZ immediates as negatives when ↵Gordon Keiser2013-03-281-2/+2
| | | | | | | | the upper bit is set. They should always be zero-extended, not sign extended. Added test case. llvm-svn: 178275
* Patch by Gordon Keiser!Joe Abbey2013-03-261-1/+1
| | | | | | | | | | If PC or SP is the destination, the disassembler erroneously failed with the invalid encoding, despite the manual saying that both are fine. This patch addresses failure to decode encoding T4 of LDR (A8.8.62) which is a postindexed load, where the offset 0xc is applied to SP after the load occurs. llvm-svn: 178017
* Remove edis - the enhanced disassembler. Fixes PR14654.Roman Divacky2012-12-191-16/+0
| | | | llvm-svn: 170578
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-6/+6
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
* Fixed the arm disassembly of invalid BFI instructions to not build a bad MCInstKevin Enderby2012-11-291-1/+7
| | | | | | which would then cause an assert when printed. rdar://11437956 llvm-svn: 168960
* Fix ARM's b.w instruction for thumb 2 and the encoding T4. The branch targetKevin Enderby2012-10-291-9/+21
| | | | | | | is 24 bits not 20 and the decoding needed to correctly handle converting the J1 and J2 bits to their I1 and I2 values to reconstruct the displacement. llvm-svn: 166982
* Fix a bug where a 32-bit address with the high bit does not get symbolicatedKevin Enderby2012-10-181-2/+3
| | | | | | | because the value is incorrectly being signed extended when passed to SymbolLookUp(). llvm-svn: 166234
* Fix the handling of edge cases in ARM shifted operands.Tim Northover2012-09-221-0/+5
| | | | | | | | | This patch fixes load/store instructions to handle less common cases like "asr #32", "rrx" properly throughout the MC layer. Patch by Chris Lidbury. llvm-svn: 164455
* Diagnose invalid alignments on duplicating VLDn instructions.Tim Northover2012-09-061-0/+4
| | | | | | Patch by Chris Lidbury. llvm-svn: 163323
* Check for invalid alignment values when decoding VLDn/VSTn (single ln) ↵Tim Northover2012-09-061-8/+38
| | | | | | | | instructions. Patch by Chris Lidbury. llvm-svn: 163321
* Fix integer undefined behavior due to signed left shift overflow in LLVM.Richard Smith2012-08-241-1/+1
| | | | | | Reviewed offline by chandlerc. llvm-svn: 162623
* Remove unnecessary include of ARMGenInstrInfo.inc.Craig Topper2012-08-171-1/+0
| | | | llvm-svn: 162086
* Switch the fixed-length disassembler to be table-driven.Jim Grosbach2012-08-141-411/+425
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Refactor the TableGen'erated fixed length disassemblmer to use a table-driven state machine rather than a massive set of nested switch() statements. As a result, the ARM Disassembler (ARMDisassembler.cpp) builds much more quickly and generates a smaller end result. For a Release+Asserts build on a 16GB 3.4GHz i7 iMac w/ SSD: Time to compile at -O2 (averaged w/ hot caches): Previous: 35.5s New: 8.9s TEXT size: Previous: 447,251 New: 297,661 Builds in 25% of the time previously required and generates code 66% of the size. Execution time of the disassembler is only slightly slower (7% disassembling 10 million ARM instructions, 19.6s vs 21.0s). The new implementation has not yet been tuned, however, so the performance should almost certainly be recoverable should it become a concern. llvm-svn: 161888
* Fix #13035, a bug around Thumb instruction LDRD/STRD with negative #0 offset ↵Jiangning Liu2012-08-021-3/+8
| | | | | | index issue. llvm-svn: 161162
* Fix #13138, a bug around ARM instruction DSB encoding and decoding issue.Jiangning Liu2012-08-021-12/+1
| | | | llvm-svn: 161161
* Fix a typo (the the => the)Sylvestre Ledru2012-07-231-1/+1
| | | | llvm-svn: 160621
* Fix instruction description of VMOV (between two ARM core registers and two ↵Richard Barton2012-07-101-4/+4
| | | | | | single-precision resiters) (and do it properly this time! llvm-svn: 159989
* Revert r159938 (and r159945) to appease the buildbots.Chad Rosier2012-07-091-4/+4
| | | | llvm-svn: 159960
* Oops - correct broken disassembly for VMOVRichard Barton2012-07-091-1/+1
| | | | llvm-svn: 159945
* Fix instruction description of VMOV (between two ARM core registers and two ↵Richard Barton2012-07-091-4/+4
| | | | | | single-precision resiters) llvm-svn: 159938
* Correct decoder for T1 conditional B encodingRichard Barton2012-06-061-2/+2
| | | | llvm-svn: 158055
* ARMDisassembler.cpp: Fix utf8 char in comments.NAKAMURA Takumi2012-05-221-3/+3
| | | | llvm-svn: 157292
* Tweak to the fix in r156212, as with the change in removing the shift theKevin Enderby2012-05-041-1/+1
| | | | | | SignExtend32<22>(Val<<1) also needs to change to SignExtend32<21>(Val) . llvm-svn: 156213
* Fix a bug in the ARM disassembler for wide branch conditional instructionsKevin Enderby2012-05-041-1/+1
| | | | | | | where the symbolic operand's displacement was incorrectly shifted left by 1. rdar://11387046 llvm-svn: 156212
* Fix issues with the ARM bl and blx thumb instructions and the J1 and J2 bitsKevin Enderby2012-05-031-4/+34
| | | | | | | | | for the assembler and disassembler. Which were not being set/read correctly for offsets greater than 22 bits in some cases. Changes to lib/Target/ARM/ARMAsmBackend.cpp from Gideon Myles! llvm-svn: 156118
* Fixed disassembler for vstm/vldm ARM VFP instructions.Silviu Baranga2012-05-031-4/+6
| | | | llvm-svn: 156077
* ARM: Tweak tADDrSP definition for consistent operand order.Jim Grosbach2012-04-271-1/+1
| | | | | | Make the operand order of the instruction match that of the asm syntax. llvm-svn: 155747
* Refactor IT handling not to store the bottom bit of the condition code in ↵Richard Barton2012-04-271-8/+3
| | | | | | the mask operand in the MCInst. llvm-svn: 155700
* Refactor Thumb ITState handling in ARM Disassembler to more efficiently use ↵Richard Barton2012-04-241-31/+69
| | | | | | its vector llvm-svn: 155439
* Added support for disassembling unpredictable swp/swpb ARM instructions.Silviu Baranga2012-04-181-0/+4
| | | | llvm-svn: 155004
* Added support for unpredictable mcrr/mcrr2/mrrc/mrrc2 ARM instruction in the ↵Silviu Baranga2012-04-181-0/+30
| | | | | | disassembler. Since the upredicability conditions are complex, C++ code was added to handle them. llvm-svn: 155001
* Fix ARM disassembly of VLD2 (single 2-element structure to all lanes)Kevin Enderby2012-04-171-7/+1
| | | | | | | instructions with writebacks. And add test a case for all opcodes handed by DecodeVLD2DupInstruction() in ARMDisassembler.cpp . llvm-svn: 154884
* Fix a few more places in the ARM disassembler so that branches getKevin Enderby2012-04-121-4/+29
| | | | | | symbolic operands added when using the C disassembler API. llvm-svn: 154628
* Fixed a case of ARM disassembly getting an assert on a bad encodingKevin Enderby2012-04-111-0/+2
| | | | | | of a VST instruction. llvm-svn: 154544
* Fix ARM disassembly of VLD instructions with writebacks.  And add test a caseKevin Enderby2012-04-111-0/+12
| | | | | | for all opcodes handed by DecodeVLDInstruction() in ARMDisassembler.cpp . llvm-svn: 154459
* ARMDisassembler: drop bogus dependency on ARMCodeGenDylan Noblesmith2012-04-032-3/+2
| | | | | | | And indirectly, a dependency on most of the core LLVM optimization libraries. llvm-svn: 153957
* Remove unnecessary llvm:: qualificationsCraig Topper2012-03-271-209/+209
| | | | llvm-svn: 153500
* Added soft fail checks for the disassembler when decoding some corner cases ↵Silviu Baranga2012-03-221-1/+81
| | | | | | of the STRD, STRH, LDRD, LDRH, LDRSH and LDRSB instructions on ARM. llvm-svn: 153252
* Added soft fail cases for the disassembler when decoding LDRSBT, LDRHT or ↵Silviu Baranga2012-03-221-3/+31
| | | | | | LDRSHT instruction on ARM llvm-svn: 153251
* Fix ARM disassembly of VST1 and VST2 instructions with writeback. And add testKevin Enderby2012-03-211-0/+19
| | | | | | case for all opcodes handed by DecodeVSTInstruction() in ARMDisassembler.cpp . llvm-svn: 153218
* The ARM instructions that have an unpredictable behavior when the pc ↵Silviu Baranga2012-03-201-2/+8
| | | | | | register operand is given now fail with soft fail. Modified the regression tests to reflect this. llvm-svn: 153089
* Use uint16_t to store registers and opcode in static tables in the target ↵Craig Topper2012-03-111-6/+6
| | | | | | specific backends. llvm-svn: 152537
* Tidy up. Remove dead code that slipped into previous commit.Jim Grosbach2012-03-071-6/+0
| | | | llvm-svn: 152184
* ARM more NEON VLD/VST composite physical register refactoring.Jim Grosbach2012-03-061-0/+7
| | | | | | Register pair, all lanes subscripting. llvm-svn: 152157
* ARM refactor more NEON VLD/VST instructions to use composite physregsJim Grosbach2012-03-061-25/+41
| | | | | | | Register pair VLD1/VLD2 all-lanes instructions. Kill off more of the pseudos as a result. llvm-svn: 152150
* Fix a bug in the ARM disassembly of the neon VLD2 all lanes instruction.Kevin Enderby2012-03-061-7/+7
| | | | llvm-svn: 152127
* ARM Refactor VLD/VST spaced pair instructions.Jim Grosbach2012-03-051-0/+50
| | | | | | Use the new composite physical registers. llvm-svn: 152063
* ARM refactor away a bunch of VLD/VST pseudo instructions.Jim Grosbach2012-03-051-6/+89
| | | | | | | | | With the new composite physical registers to represent arbitrary pairs of DPR registers, we don't need the pseudo-registers anymore. Get rid of a bunch of them that use DPR register pairs and just use the real instructions directly instead. llvm-svn: 152045
* Make MemoryObject accessor members const againDerek Schuff2012-02-291-4/+4
| | | | llvm-svn: 151687
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