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* ARM: fix CPS decoding when ambiguous with QADDAmaury de la Vieuville2013-06-081-0/+32
| | | | | | | | | Handle the case when the disassembler table can't tell the difference between some encodings of QADD and CPS. Add some necessary safe guards in CPS decoding as well. llvm-svn: 183610
* ARM: fix VCVT decodingAmaury de la Vieuville2013-06-081-2/+2
| | | | | | UNPRED was reported instead of UNDEF llvm-svn: 183608
* ARM: add fstmx and fldmx instructions for assemblyTim Northover2013-05-311-2/+15
| | | | | | | | | These instructions are deprecated oddities, but we still need to be able to disassemble (and reassemble) them if and when they're encountered. Patch by Amaury de la Vieuville. llvm-svn: 183011
* Replace Count{Leading,Trailing}Zeros_{32,64} with count{Leading,Trailing}Zeros.Michael J. Spencer2013-05-241-1/+1
| | | | llvm-svn: 182680
* Remove the Copied parameter from MemoryObject::readBytes.Benjamin Kramer2013-05-241-3/+3
| | | | | | | | | | There was exactly one caller using this API right, the others were relying on specific behavior of the default implementation. Since it's too hard to use it right just remove it and standardize on the default behavior. Defines away PR16132. llvm-svn: 182636
* Add MCSymbolizer for symbolic/annotated disassembly.Ahmed Bougacha2013-05-241-107/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a basic first step towards symbolization of disassembled instructions. This used to be done using externally provided (C API) callbacks. This patch introduces: - the MCSymbolizer class, that mimics the same functions that were used in the X86 and ARM disassemblers to symbolize immediate operands and to annotate loads based off PC (for things like c string literals). - the MCExternalSymbolizer class, which implements the old C API. - the MCRelocationInfo class, which provides a way for targets to translate relocations (either object::RelocationRef, or disassembler C API VariantKinds) to MCExprs. - the MCObjectSymbolizer class, which does symbolization using what it finds in an object::ObjectFile. This makes simple symbolization (with no fancy relocation stuff) work for all object formats! - x86-64 Mach-O and ELF MCRelocationInfos. - A basic ARM Mach-O MCRelocationInfo, that provides just enough to support the C API VariantKinds. Most of what works in otool (the only user of the old symbolization API that I know of) for x86-64 symbolic disassembly (-tvV) works, namely: - symbol references: call _foo; jmp 15 <_foo+50> - relocations: call _foo-_bar; call _foo-4 - __cf?string: leaq 193(%rip), %rax ## literal pool for "hello" Stub support is the main missing part (because libObject doesn't know, among other things, about mach-o indirect symbols). As for the MCSymbolizer API, instead of relying on the disassemblers to call the tryAdding* methods, maybe this could be done automagically using InstrInfo? For instance, even though PC-relative LEAs are used to get the address of string literals in a typical Mach-O file, a MOV would be used in an ELF file. And right now, the explicit symbolization only recognizes PC-relative LEAs. InstrInfo should have already have most of what is needed to know what to symbolize, so this can definitely be improved. I'd also like to remove object::RelocationRef::getValueString (it seems only used by relocation printing in objdump), as simply printing the created MCExpr is definitely enough (and cleaner than string concats). llvm-svn: 182625
* VSTn instructions have a number of encoding constraints which are not ↵Mihai Popa2013-05-201-0/+51
| | | | | | implemented. I have added these using wrapper methods around the original custom decoder (incidentally - this is a huge poorly written method that should be cleaned up. I have left it as is since the changes would be much to hard to review). llvm-svn: 182281
* Q registers are encoded in fields of the same length as D registers. As Q ↵Mihai Popa2013-05-201-1/+1
| | | | | | registers are half as many, the ARM reference manual mandates the least significant bit to be zeroed out. Failure to do so should result in an undefined instruction. With this change test/MC/Disassembler/ARM/invalid-VQADD-arm.txt is passing (removed XFAIL). llvm-svn: 182279
* Replace some bit operations with simpler ones. No functionality change.Benjamin Kramer2013-05-191-1/+1
| | | | llvm-svn: 182226
* The purpose of the patch is to fix the syntax of ARM mrc and mrc2 ↵Mihai Popa2013-05-131-0/+18
| | | | | | instructions when they are used to write to the APSR. In this case, the destination operand should be APSR_nzcv, and the encoding of the target should be 0b1111 (same as for PC). In pre-UAL syntax, this form used the PC register as a textual target. This is still allowed for backward compatibility. llvm-svn: 181705
* ARM: Fix encoding of hint instruction for Thumb.Quentin Colombet2013-04-261-4/+6
| | | | | | | | | | | | | | | "hint" space for Thumb actually overlaps the encoding space of the CPS instruction. In actuality, hints can be defined as CPS instructions where imod and M bits are all nil. Handle decoding of permitted nop-compatible hints (i.e. nop, yield, wfi, wfe, sev) in DecodeT2CPSInstruction. This commit adds a proper diagnostic message for Imm0_4 and updates all tests. Patch by Mihail Popa <Mihail.Popa@arm.com>. llvm-svn: 180617
* ARM: Permit "sp" in ARM variant of STREXD instructionsTim Northover2013-04-191-1/+1
| | | | | | Patch from Mihail Popa llvm-svn: 179854
* ARM: permit "sp" in ARM variants of MOVW/MOVT instructionsTim Northover2013-04-191-2/+3
| | | | llvm-svn: 179847
* Fix treatment of ARM unallocated hint instructions.Quentin Colombet2013-04-171-0/+11
| | | | | | | | | | | | | | | The reference manual defines only 5 permitted values for the immediate field of the "hint" instruction: 1. nop (imm == 0) 2. yield (imm == 1) 3. wfe (imm == 2) 4. wfi (imm == 3) 5. sev (imm == 4) Therefore, restrict the permitted values for the "hint" instruction to 0 through 4. Patch by Mihail Popa <Mihail.Popa@arm.com> llvm-svn: 179707
* Fix issue with disassembler decoding CBZ/CBNZ immediates as negatives when ↵Gordon Keiser2013-03-281-2/+2
| | | | | | | | the upper bit is set. They should always be zero-extended, not sign extended. Added test case. llvm-svn: 178275
* Patch by Gordon Keiser!Joe Abbey2013-03-261-1/+1
| | | | | | | | | | If PC or SP is the destination, the disassembler erroneously failed with the invalid encoding, despite the manual saying that both are fine. This patch addresses failure to decode encoding T4 of LDR (A8.8.62) which is a postindexed load, where the offset 0xc is applied to SP after the load occurs. llvm-svn: 178017
* Remove edis - the enhanced disassembler. Fixes PR14654.Roman Divacky2012-12-191-16/+0
| | | | llvm-svn: 170578
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-6/+6
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
* Fixed the arm disassembly of invalid BFI instructions to not build a bad MCInstKevin Enderby2012-11-291-1/+7
| | | | | | which would then cause an assert when printed. rdar://11437956 llvm-svn: 168960
* Fix ARM's b.w instruction for thumb 2 and the encoding T4. The branch targetKevin Enderby2012-10-291-9/+21
| | | | | | | is 24 bits not 20 and the decoding needed to correctly handle converting the J1 and J2 bits to their I1 and I2 values to reconstruct the displacement. llvm-svn: 166982
* Fix a bug where a 32-bit address with the high bit does not get symbolicatedKevin Enderby2012-10-181-2/+3
| | | | | | | because the value is incorrectly being signed extended when passed to SymbolLookUp(). llvm-svn: 166234
* Fix the handling of edge cases in ARM shifted operands.Tim Northover2012-09-221-0/+5
| | | | | | | | | This patch fixes load/store instructions to handle less common cases like "asr #32", "rrx" properly throughout the MC layer. Patch by Chris Lidbury. llvm-svn: 164455
* Diagnose invalid alignments on duplicating VLDn instructions.Tim Northover2012-09-061-0/+4
| | | | | | Patch by Chris Lidbury. llvm-svn: 163323
* Check for invalid alignment values when decoding VLDn/VSTn (single ln) ↵Tim Northover2012-09-061-8/+38
| | | | | | | | instructions. Patch by Chris Lidbury. llvm-svn: 163321
* Fix integer undefined behavior due to signed left shift overflow in LLVM.Richard Smith2012-08-241-1/+1
| | | | | | Reviewed offline by chandlerc. llvm-svn: 162623
* Remove unnecessary include of ARMGenInstrInfo.inc.Craig Topper2012-08-171-1/+0
| | | | llvm-svn: 162086
* Switch the fixed-length disassembler to be table-driven.Jim Grosbach2012-08-141-411/+425
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Refactor the TableGen'erated fixed length disassemblmer to use a table-driven state machine rather than a massive set of nested switch() statements. As a result, the ARM Disassembler (ARMDisassembler.cpp) builds much more quickly and generates a smaller end result. For a Release+Asserts build on a 16GB 3.4GHz i7 iMac w/ SSD: Time to compile at -O2 (averaged w/ hot caches): Previous: 35.5s New: 8.9s TEXT size: Previous: 447,251 New: 297,661 Builds in 25% of the time previously required and generates code 66% of the size. Execution time of the disassembler is only slightly slower (7% disassembling 10 million ARM instructions, 19.6s vs 21.0s). The new implementation has not yet been tuned, however, so the performance should almost certainly be recoverable should it become a concern. llvm-svn: 161888
* Fix #13035, a bug around Thumb instruction LDRD/STRD with negative #0 offset ↵Jiangning Liu2012-08-021-3/+8
| | | | | | index issue. llvm-svn: 161162
* Fix #13138, a bug around ARM instruction DSB encoding and decoding issue.Jiangning Liu2012-08-021-12/+1
| | | | llvm-svn: 161161
* Fix a typo (the the => the)Sylvestre Ledru2012-07-231-1/+1
| | | | llvm-svn: 160621
* Fix instruction description of VMOV (between two ARM core registers and two ↵Richard Barton2012-07-101-4/+4
| | | | | | single-precision resiters) (and do it properly this time! llvm-svn: 159989
* Revert r159938 (and r159945) to appease the buildbots.Chad Rosier2012-07-091-4/+4
| | | | llvm-svn: 159960
* Oops - correct broken disassembly for VMOVRichard Barton2012-07-091-1/+1
| | | | llvm-svn: 159945
* Fix instruction description of VMOV (between two ARM core registers and two ↵Richard Barton2012-07-091-4/+4
| | | | | | single-precision resiters) llvm-svn: 159938
* Correct decoder for T1 conditional B encodingRichard Barton2012-06-061-2/+2
| | | | llvm-svn: 158055
* ARMDisassembler.cpp: Fix utf8 char in comments.NAKAMURA Takumi2012-05-221-3/+3
| | | | llvm-svn: 157292
* Tweak to the fix in r156212, as with the change in removing the shift theKevin Enderby2012-05-041-1/+1
| | | | | | SignExtend32<22>(Val<<1) also needs to change to SignExtend32<21>(Val) . llvm-svn: 156213
* Fix a bug in the ARM disassembler for wide branch conditional instructionsKevin Enderby2012-05-041-1/+1
| | | | | | | where the symbolic operand's displacement was incorrectly shifted left by 1. rdar://11387046 llvm-svn: 156212
* Fix issues with the ARM bl and blx thumb instructions and the J1 and J2 bitsKevin Enderby2012-05-031-4/+34
| | | | | | | | | for the assembler and disassembler. Which were not being set/read correctly for offsets greater than 22 bits in some cases. Changes to lib/Target/ARM/ARMAsmBackend.cpp from Gideon Myles! llvm-svn: 156118
* Fixed disassembler for vstm/vldm ARM VFP instructions.Silviu Baranga2012-05-031-4/+6
| | | | llvm-svn: 156077
* ARM: Tweak tADDrSP definition for consistent operand order.Jim Grosbach2012-04-271-1/+1
| | | | | | Make the operand order of the instruction match that of the asm syntax. llvm-svn: 155747
* Refactor IT handling not to store the bottom bit of the condition code in ↵Richard Barton2012-04-271-8/+3
| | | | | | the mask operand in the MCInst. llvm-svn: 155700
* Refactor Thumb ITState handling in ARM Disassembler to more efficiently use ↵Richard Barton2012-04-241-31/+69
| | | | | | its vector llvm-svn: 155439
* Added support for disassembling unpredictable swp/swpb ARM instructions.Silviu Baranga2012-04-181-0/+4
| | | | llvm-svn: 155004
* Added support for unpredictable mcrr/mcrr2/mrrc/mrrc2 ARM instruction in the ↵Silviu Baranga2012-04-181-0/+30
| | | | | | disassembler. Since the upredicability conditions are complex, C++ code was added to handle them. llvm-svn: 155001
* Fix ARM disassembly of VLD2 (single 2-element structure to all lanes)Kevin Enderby2012-04-171-7/+1
| | | | | | | instructions with writebacks. And add test a case for all opcodes handed by DecodeVLD2DupInstruction() in ARMDisassembler.cpp . llvm-svn: 154884
* Fix a few more places in the ARM disassembler so that branches getKevin Enderby2012-04-121-4/+29
| | | | | | symbolic operands added when using the C disassembler API. llvm-svn: 154628
* Fixed a case of ARM disassembly getting an assert on a bad encodingKevin Enderby2012-04-111-0/+2
| | | | | | of a VST instruction. llvm-svn: 154544
* Fix ARM disassembly of VLD instructions with writebacks.  And add test a caseKevin Enderby2012-04-111-0/+12
| | | | | | for all opcodes handed by DecodeVLDInstruction() in ARMDisassembler.cpp . llvm-svn: 154459
* ARMDisassembler: drop bogus dependency on ARMCodeGenDylan Noblesmith2012-04-032-3/+2
| | | | | | | And indirectly, a dependency on most of the core LLVM optimization libraries. llvm-svn: 153957
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