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* ARM NEON refactor VST2 w/ writeback instructions.Jim Grosbach2011-12-141-9/+18
| | | | | | | In addition to improving the representation, this adds support for assembly parsing of these instructions. llvm-svn: 146588
* ARM NEON VST2 assembly parsing and encoding.Jim Grosbach2011-12-141-30/+0
| | | | | | | | Work in progress. Parsing for non-writeback, single spaced register lists works now. The rest have the representations better factored, but still need more to be able to parse properly. llvm-svn: 146579
* LLVMBuild: Remove trailing newline, which irked me.Daniel Dunbar2011-12-121-1/+0
| | | | llvm-svn: 146409
* ARM assembly parsing and encoding for VLD2 with writeback.Jim Grosbach2011-12-091-9/+18
| | | | | | | | | | | Refactor the instructions into fixed writeback and register-stride writeback variants to simplify the offset operand (no more optional register operand using reg0). This is a simpler representation and allows the assembly parser to more easily handle these instructions. Add tests for the instruction variants now supported. llvm-svn: 146278
* Remove unused variableMatt Beaumont-Gay2011-11-301-2/+0
| | | | llvm-svn: 145517
* ARM parsing for VLD1 all lanes, with writeback.Jim Grosbach2011-11-301-10/+6
| | | | llvm-svn: 145510
* ARM assembly parsing and encoding for four-register VST1.Jim Grosbach2011-11-291-28/+8
| | | | llvm-svn: 145450
* ARM assembly parsing and encoding for three-register VST1.Jim Grosbach2011-11-291-20/+8
| | | | llvm-svn: 145442
* build/CMake: Finish removal of add_llvm_library_dependencies.Daniel Dunbar2011-11-291-8/+0
| | | | llvm-svn: 145420
* Fix a misplaced paren bug.Owen Anderson2011-11-151-1/+1
| | | | llvm-svn: 144692
* Fix an ambiguous decoding where we failed to properly decode VMOVv2f32 and ↵Owen Anderson2011-11-151-8/+62
| | | | | | VMOVv4f32. llvm-svn: 144683
* build: Attempt to rectify inconsistencies between CMake and LLVMBuild ↵Daniel Dunbar2011-11-121-1/+1
| | | | | | | | versions of explicit dependencies. - The hope is that we have a tool/test to verify these are accurate (and tight) soon. llvm-svn: 144444
* Re-apply 144430, this time with the associated isel and disassmbler bits.Jim Grosbach2011-11-121-4/+0
| | | | | | Original commit msg: 'ARM assembly parsing for VST1 two-register encoding.' llvm-svn: 144437
* Remove the unnecessary dependency on libARMCodeGen from libARMDisassembler.Benjamin Kramer2011-11-111-1/+1
| | | | llvm-svn: 144384
* build: Add initial cut at LLVMBuild.txt files.Daniel Dunbar2011-11-031-0/+24
| | | | llvm-svn: 143634
* The rules disallowing single-register reglist operands only apply to the POP ↵Owen Anderson2011-11-021-5/+1
| | | | | | alias, not to LDM/STM instructions. Revert r143552. llvm-svn: 143553
* Register list operands are not allowed to contain only a single register. ↵Owen Anderson2011-11-021-1/+5
| | | | | | Alternate encodings are used in that case. llvm-svn: 143552
* Fix disassembly of some VST1 instructions.Owen Anderson2011-11-011-5/+19
| | | | llvm-svn: 143507
* ARM VST1 w/ writeback assembly parsing and encoding.Jim Grosbach2011-10-311-12/+16
| | | | llvm-svn: 143369
* More not-crashing NEON disassembly updates for the vld refactoring.Owen Anderson2011-10-311-0/+4
| | | | llvm-svn: 143351
* Reapply r143202, with a manual decoding hook for SWP. This change ↵Owen Anderson2011-10-281-0/+24
| | | | | | inadvertantly exposed a decoding ambiguity between SWP and CPS that the auto-generated decoder can't handle. llvm-svn: 143208
* Add some NEON stores to the VLD decoding hook that were accidentally omitted ↵Owen Anderson2011-10-271-0/+4
| | | | | | previously. llvm-svn: 143162
* ARM assembly parsing and encoding for VLD1 with writeback.Jim Grosbach2011-10-251-4/+8
| | | | | | Four entry register lists. llvm-svn: 142882
* ARM assembly parsing and encoding for VLD1 w/ writeback.Jim Grosbach2011-10-241-4/+8
| | | | | | Three entry register list variation. llvm-svn: 142876
* ARM refactor am6offset usage for VLD1.Jim Grosbach2011-10-241-12/+51
| | | | | | | | Split am6offset into fixed and register offset variants so the instruction encodings are explicit rather than relying an a magic reg0 marker. Needed to being able to parse these. llvm-svn: 142853
* Fix a NEON disassembly case that was broken in the recent refactorings. As ↵Owen Anderson2011-10-241-6/+0
| | | | | | more of this code gets refactored, a lot of these manual decoding hooks should get smaller and/or go away entirely. llvm-svn: 142817
* Move various generated tables into read-only memory, fixing up const ↵Benjamin Kramer2011-10-221-1/+1
| | | | | | correctness along the way. llvm-svn: 142726
* Assembly parsing for 4-register sequential variant of VLD2.Jim Grosbach2011-10-211-18/+0
| | | | llvm-svn: 142704
* Assembly parsing for 2-register sequential variant of VLD2.Jim Grosbach2011-10-211-6/+0
| | | | llvm-svn: 142691
* Assembly parsing for 4-register variant of VLD1.Jim Grosbach2011-10-211-24/+0
| | | | llvm-svn: 142682
* Assembly parsing for 3-register variant of VLD1.Jim Grosbach2011-10-211-16/+0
| | | | llvm-svn: 142675
* ARM VLD parsing and encoding.Jim Grosbach2011-10-211-8/+0
| | | | | | | | | | | | Next step in the ongoing saga of NEON load/store assmebly parsing. Handle VLD1 instructions that take a two-register register list. Adjust the instruction definitions to only have the single encoded register as an operand. The super-register from the pseudo is kept as an implicit def, so passes which come after pseudo-expansion still know that the instruction defines the other subregs. llvm-svn: 142670
* Tidy up. Trailing whitespace.Jim Grosbach2011-10-201-2/+2
| | | | llvm-svn: 142591
* Removed set, but unused variables.Chad Rosier2011-10-171-10/+0
| | | | | | Patch by Joe Abbey <jabbey@arxan.com>. llvm-svn: 142223
* Fix a non-firing assert. Change:Richard Trieu2011-10-141-1/+1
| | | | | | | | assert("bad SymbolicOp.VariantKind"); To: assert(0 && "bad SymbolicOp.VariantKind"); llvm-svn: 142000
* Fix undefined shift. Patch by Ahmed Charles.Eli Friedman2011-10-131-1/+1
| | | | llvm-svn: 141914
* SETEND is not allowed in an IT block.Owen Anderson2011-10-131-0/+1
| | | | llvm-svn: 141874
* ARM addrmode5 represents the 'U' bit of the encoding backwards.Jim Grosbach2011-10-121-14/+17
| | | | | | | The disassembler needs to use the AM5 factory methods instead of just building up the immediate directly. llvm-svn: 141819
* Thumb2 assembly parsing and encoding for LDC/STC.Jim Grosbach2011-10-121-24/+50
| | | | llvm-svn: 141811
* addrmode2 is gone from these, so no need for the reg0 operand.Jim Grosbach2011-10-121-24/+0
| | | | llvm-svn: 141794
* Fix the check for nested IT instructions in the disassembler. We need to ↵Owen Anderson2011-10-061-3/+6
| | | | | | perform the check before adding the Thumb predicate, which pops on entry off the ITBlock queue. llvm-svn: 141339
* Adding back support for printing operands symbolically to ARM's new disassemblerKevin Enderby2011-10-041-3/+211
| | | | | | | | | | | | | | | | | | | using llvm's public 'C' disassembler API now including annotations. Hooked this up to Darwin's otool(1) so it can again print things like branch targets for example this: blx _puts instead of this: blx #-36 and includes support for annotations for branches to symbol stubs like: bl 0x40 @ symbol stub for: _puts and annotations for pc relative loads like this: ldr r3, #8 @ literal pool for: Hello, world! Also again can print the expression encoded in the Mach-O relocation entries for things like this: movt r0, :upper16:((_foo-_bar)+1234) llvm-svn: 141129
* ARM fix encoding of VMOV.f32 and VMOV.f64 immediates.Jim Grosbach2011-09-301-27/+0
| | | | | | | | | | | Encode the immediate into its 8-bit form as part of isel rather than later, which simplifies things for mapping the encoding bits, allows the removal of the custom disassembler decoding hook, makes the operand printer trivial, and prepares things more cleanly for handling these in the asm parser. rdar://10211428 llvm-svn: 140834
* ASR #32 is not allowed on Thumb2 USAT and SSAT instructions.Owen Anderson2011-09-261-0/+14
| | | | llvm-svn: 140560
* Reapply r140412 (Thumb2 reg-reg loads cannot target SP or PC), with invalid ↵Owen Anderson2011-09-231-1/+1
| | | | | | testcases updated. llvm-svn: 140415
* Revert r140412. This affects more instructions than intended.Owen Anderson2011-09-231-1/+1
| | | | llvm-svn: 140413
* Thumb2 register-shifted-register loads cannot target the PC or the SP.Owen Anderson2011-09-231-1/+1
| | | | llvm-svn: 140412
* tMOVSr is not allowed in an IT block either.Owen Anderson2011-09-191-0/+1
| | | | llvm-svn: 140104
* CPS instructions are UNPREDICTABLE inside IT blocks.Owen Anderson2011-09-191-0/+4
| | | | llvm-svn: 140102
* Thumb2 TBB and TBH instructions are only allowed at the end of IT blocks, ↵Owen Anderson2011-09-191-0/+2
| | | | | | not in the middle. llvm-svn: 140079
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