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path: root/llvm/lib/Target/ARM/AsmPrinter/ARMInstPrinter.h
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* Rename the AsmPrinter directory to InstPrinter for those targets that haveJim Grosbach2010-10-011-117/+0
| | | | | | | been MC-ized for assembly printing. MSP430 is mostly so, but still has the asm printer and lowering code in the printer subdir for the moment. llvm-svn: 115360
* Now that the pseudos that needed this are all custom lowered, we can go backJim Grosbach2010-09-301-1/+1
| | | | | | to an empty PrintSpecial() llvm-svn: 115128
* nuke unused varJim Grosbach2010-09-231-1/+0
| | | | llvm-svn: 114676
* Add PrintSpecial() handling for in ARM MC instruction printer.Jim Grosbach2010-09-221-2/+1
| | | | llvm-svn: 114563
* Add start of support for MC instruction printer of ARM jump tables. Filling inJim Grosbach2010-09-211-0/+2
| | | | | | the rest of it is next up. llvm-svn: 114500
* Hook up verbose asm comment printing for SOImm operands in MC printerJim Grosbach2010-09-171-2/+1
| | | | llvm-svn: 114215
* trailing whitespaceJim Grosbach2010-09-171-8/+8
| | | | llvm-svn: 114212
* Rename sat_shift operand to shift_imm, in preparation for using it for otherBob Wilson2010-08-161-1/+1
| | | | | | instructions besides saturate instructions. No functional changes. llvm-svn: 111168
* Cleaned up the for-disassembly-only entries in the arm instruction table so thatJohnny Chen2010-08-121-0/+1
| | | | | | | the memory barrier variants (other than 'SY' full system domain read and write) are treated as one instruction with option operand. llvm-svn: 110951
* Move the ARM SSAT and USAT optional shift amount operand out of theBob Wilson2010-08-111-0/+1
| | | | | | instruction opcode. This also fixes part of PR7792. llvm-svn: 110875
* Add instruction encoding for the Neon VMOV immediate instruction. This changesBob Wilson2010-06-111-4/+1
| | | | | | | | | | | the machine instruction representation of the immediate value to be encoded into an integer with similar fields as the actual VMOV instruction. This makes things easier for the disassembler, since it can just stuff the bits into the immediate operand, but harder for the asm printer since it has to decode the value to be printed. Testcase for the encoding will follow later when MC has more support for ARM. llvm-svn: 105836
* Fixed a bug in DisassembleN1RegModImmFrm() where a break stmt was missing for aJohnny Chen2010-04-161-4/+4
| | | | | | | | | | case. Also, the 0xFF hex literal involved in the shift for ESize64 should be suffixed "ul" to preserve the shift result. Implemented printHex*ImmOperand() by copying from ARMAsmPrinter.cpp and added a test case for DisassembleN1RegModImmFrm()/printHex64ImmOperand(). llvm-svn: 101557
* fix an ugly wart in the MCInstPrinter api where theChris Lattner2010-04-041-3/+3
| | | | | | | | raw_ostream to print an instruction to had to be specified at MCInstPrinter construction time instead of being able to pick at each call to printInstruction. llvm-svn: 100307
* change a ton of code to not implicitly use the "O" raw_ostreamChris Lattner2010-04-041-50/+67
| | | | | | member of AsmPrinter. Instead, pass it in explicitly. llvm-svn: 100306
* Re-commit r98683 ("remove redundant writeback flag from ARM address mode 6")Bob Wilson2010-03-201-0/+1
| | | | | | | with changes to add a separate optional register update argument. Change all the NEON instructions with address register writeback to use it. llvm-svn: 99095
* Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrmJohnny Chen2010-03-171-20/+20
| | | | | | | | | | | | | instructions to help disassembly. We also changed the output of the addressing modes to omit the '+' from the assembler syntax #+/-<imm> or +/-<Rm>. See, for example, A8.6.57/58/60. And modified test cases to not expect '+' in +reg or #+num. For example, ; CHECK: ldr.w r9, [r7, #28] llvm-svn: 98745
* --- Reverse-merging r98637 into '.':Bob Wilson2010-03-161-20/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U test/CodeGen/ARM/tls2.ll U test/CodeGen/ARM/arm-negative-stride.ll U test/CodeGen/ARM/2009-10-30.ll U test/CodeGen/ARM/globals.ll U test/CodeGen/ARM/str_pre-2.ll U test/CodeGen/ARM/ldrd.ll U test/CodeGen/ARM/2009-10-27-double-align.ll U test/CodeGen/Thumb2/thumb2-strb.ll U test/CodeGen/Thumb2/ldr-str-imm12.ll U test/CodeGen/Thumb2/thumb2-strh.ll U test/CodeGen/Thumb2/thumb2-ldr.ll U test/CodeGen/Thumb2/thumb2-str_pre.ll U test/CodeGen/Thumb2/thumb2-str.ll U test/CodeGen/Thumb2/thumb2-ldrh.ll U utils/TableGen/TableGen.cpp U utils/TableGen/DisassemblerEmitter.cpp D utils/TableGen/RISCDisassemblerEmitter.h D utils/TableGen/RISCDisassemblerEmitter.cpp U Makefile.rules U lib/Target/ARM/ARMInstrNEON.td U lib/Target/ARM/Makefile U lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp U lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp U lib/Target/ARM/AsmPrinter/ARMInstPrinter.h D lib/Target/ARM/Disassembler U lib/Target/ARM/ARMInstrFormats.td U lib/Target/ARM/ARMAddressingModes.h U lib/Target/ARM/Thumb2ITBlockPass.cpp llvm-svn: 98640
* Initial ARM/Thumb disassembler check-in. It consists of a tablgen backendJohnny Chen2010-03-161-20/+20
| | | | | | | | | | | | | | | | | | (RISCDisassemblerEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrm instructions to help disassembly. We also changed the output of the addressing modes to omit the '+' from the assembler syntax #+/-<imm> or +/-<Rm>. See, for example, A8.6.57/58/60. And modified test cases to not expect '+' in +reg or #+num. For example, ; CHECK: ldr.w r9, [r7, #28] llvm-svn: 98637
* Added Thumb2 LDRD/STRD pre/post variants for disassembly only.Johnny Chen2010-03-111-0/+1
| | | | | | Plus fixed the encoding of t2LDRDpci such that P = 1 and W = 0 (offset mode). llvm-svn: 98217
* Factored out the disassembly printing of CPS option, MSR mask, and Negative ZeroJohnny Chen2010-03-101-1/+4
| | | | | | | operands into their own PrintMethod, in order not to pollute the printOperand() impl with disassembly only Imm modifiers. llvm-svn: 98172
* AL is an optional mnemonic extension for always, except in IT instructions.Johnny Chen2010-03-021-0/+1
| | | | | | | Add printMandatoryPredicateOperand() PrintMethod for IT predicate printing. Ref: A8.3 Conditional execution llvm-svn: 97571
* More consistent thumb1 asm printing.Evan Cheng2009-11-191-1/+2
| | | | llvm-svn: 89328
* Print VMOV (immediate) operands as hexadecimal values. Apple's assemblerBob Wilson2009-11-061-0/+4
| | | | | | | | | will not accept negative values for these. LLVM's default operand printing sign extends values, so that valid unsigned values appear as negative immediates. Print all VMOV immediate operands as hex values to resolve this. Radar 7372576. llvm-svn: 86301
* Use fconsts and fconstd to materialize small fp constants.Evan Cheng2009-10-281-0/+2
| | | | llvm-svn: 85362
* tidyChris Lattner2009-10-211-1/+1
| | | | llvm-svn: 84738
* implement some more easy hooks.Chris Lattner2009-10-201-3/+4
| | | | llvm-svn: 84614
* Implement some hooks, make printOperand abort if unknown modifiers areChris Lattner2009-10-201-5/+5
| | | | | | present. llvm-svn: 84613
* add supprort for the 'sbit' operand, MOVi apparently has one.Chris Lattner2009-10-201-1/+1
| | | | llvm-svn: 84577
* add support for instruction predicates.Chris Lattner2009-10-201-1/+1
| | | | llvm-svn: 84575
* implement printSORegOperand, add lowering for the nasty and despicable ↵Chris Lattner2009-10-201-3/+2
| | | | | | MOVi2pieces :) llvm-svn: 84573
* lower the ARM::CONSTPOOL_ENTRY pseudo op, giving us constant pool entriesChris Lattner2009-10-191-1/+1
| | | | | | | | | | | | | like: @ BB#1: .align 2 LCPI1_0: .long L_.str-(LPC0+8) Note that proper indentation of the label :) llvm-svn: 84558
* add MCInstLower support for lowering ARM::PICADD, a pseudo op for pic stuffola.Chris Lattner2009-10-191-4/+3
| | | | llvm-svn: 84553
* add register list and hacked up addrmode #4 support, we now get this:Chris Lattner2009-10-191-2/+2
| | | | | | | | | | | | | | | | | | _main: stmsp! sp!, {r7, lr} mov r7, sp sub sp, sp, #4 mov r0, #0 str r0, [sp] ldr r0, LCPI1_0 bl _printf ldr r0, [sp] mov sp, r7 ldmsp! sp!, {r7, pc} Note the unhappy ldm/stm because of modifiers being ignored. llvm-svn: 84546
* add addrmode2 support, getting us up to:Chris Lattner2009-10-191-1/+1
| | | | | | | | | | | | | | | | _main: stm , mov r7, sp sub sp, sp, #4 mov r0, #0 str r0, [sp] ldr r0, LCPI1_0 bl _printf ldr r0, [sp] mov sp, r7 ldm , llvm-svn: 84543
* add printing support for SOImm operands, getting us to:Chris Lattner2009-10-191-2/+6
| | | | | | | | | | | _main: stm , mov r7, sp sub sp, sp, #4 mov r0, #0 str r0, llvm-svn: 84535
* wire up some basic printOperand goodness, giving us stuff like this beforeChris Lattner2009-10-191-1/+1
| | | | | | | | | | | | | we abort: _main: stm , mov r7, sp sub sp, sp, mov r0, str r0, llvm-svn: 84532
* stub out a minimal ARMInstPrinter.Chris Lattner2009-10-191-0/+86
llvm-svn: 84527
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