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path: root/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
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* ARM refactor simple immediate asm operand render methods.Jim Grosbach2011-11-121-60/+0
| | | | | | | These immediate operands all use the same simple logic for rendering to MCInst, so have them share the method for doing so. llvm-svn: 144439
* ARM vldm and vstm VFP instructions can take a data type suffix.Jim Grosbach2011-11-111-0/+22
| | | | | | | | | | | | It's ignored by the assembler when present, but is legal syntax. Other instructions have something similar, but for some mnemonics it's only sometimes not significant, so this quick check in the parser will need refactored into something more robust soon-ish. This gets some basics working in the meantime. Partial for rdar://10435264 llvm-svn: 144422
* Nuke no longer accurate comment.Jim Grosbach2011-11-111-3/+0
| | | | llvm-svn: 144411
* ARM allow Q registers in vldm/vstm register lists.Jim Grosbach2011-11-111-27/+45
| | | | | | rdar://9672822 llvm-svn: 144407
* Thumb2 ldm/stm updating w/ one register in the list are LDR/STR.Jim Grosbach2011-11-101-0/+32
| | | | | | rdar://10429490 llvm-svn: 144338
* ARM let processInstruction() tranforms chain.Jim Grosbach2011-11-101-15/+37
| | | | llvm-svn: 144337
* Thumb2 parsing for push/pop w/ hi registers in the reglist.Jim Grosbach2011-11-101-2/+32
| | | | | | rdar://10130228. llvm-svn: 144331
* Thumb1 diagnostics for reglist on PUSH/POP fix.Jim Grosbach2011-11-101-2/+2
| | | | | | Was not checking the first register in the register list. llvm-svn: 144329
* Thumb MUL assembly parsing for 3-operand form.Jim Grosbach2011-11-101-7/+9
| | | | | | | | | Get the source register that isn't tied to the destination register correct, even when the assembly source operand order is backwards. rdar://10428630 llvm-svn: 144322
* ARM .thumb_func directive for quoted symbol names.Jim Grosbach2011-11-101-3/+3
| | | | | | | | | Use the getIdentifier() method of the token, not getString(), otherwise we keep the quotes as part of the symbol name, which we don't want. rdar://10428015 llvm-svn: 144315
* ARM assembly parsing for LSR/LSL/ROR(immediate).Jim Grosbach2011-11-101-5/+32
| | | | | | More of rdar://9704684 llvm-svn: 144301
* ARM assembly parsing for ASR(immediate).Jim Grosbach2011-11-101-0/+15
| | | | | | Start of rdar://9704684 llvm-svn: 144293
* Replace (Lower|Upper)caseString in favor of StringRef's newest methods.Benjamin Kramer2011-11-061-8/+5
| | | | llvm-svn: 143891
* ARM label operands can be quoted.Jim Grosbach2011-11-011-0/+1
| | | | | | For example, labels from Objective-C sources. llvm-svn: 143511
* ARM label operands can have an optional '#' before them.Jim Grosbach2011-11-011-6/+4
| | | | llvm-svn: 143510
* ARM VLD/VST assembly parsing for symbolic address operands.Jim Grosbach2011-11-011-1/+15
| | | | llvm-svn: 143413
* ARM VST1 w/ writeback assembly parsing and encoding.Jim Grosbach2011-10-311-0/+34
| | | | llvm-svn: 143369
* ARM mode 'mov' to 'mvn' assembler alias.Jim Grosbach2011-10-281-0/+16
| | | | llvm-svn: 143237
* Add Thumb2 alias for "mov Rd, #imm" to "mvn Rd, #~imm".Jim Grosbach2011-10-281-0/+16
| | | | | | | | | | | When '~imm' is encodable as a t2_so_imm but plain 'imm' is not. For example, mov r2, #-3 becomes mvn r2, #2 rdar://10349224 llvm-svn: 143235
* ARM Allow 'q' registers in VLD/VST vector lists.Jim Grosbach2011-10-281-4/+47
| | | | | | | | Just treat it as if the constituent D registers where specified. rdar://10348896 llvm-svn: 143167
* Thumb2 ldr pc-relative encoding fixes.Jim Grosbach2011-10-261-6/+0
| | | | | | | | | We were parsing label references to the i12 encoding, which isn't right. They need to go to the pci variant instead. More of rdar://10348687 llvm-svn: 143068
* ARM parse parenthesized expressions for label references.Jim Grosbach2011-10-261-0/+1
| | | | | | Partial fix for rdar://10348687. llvm-svn: 143063
* ARM assembly parsing and encoding for VLD1 w/ writeback.Jim Grosbach2011-10-241-0/+34
| | | | | | One and two length register list variants. llvm-svn: 142861
* Move various generated tables into read-only memory, fixing up const ↵Benjamin Kramer2011-10-221-8/+9
| | | | | | correctness along the way. llvm-svn: 142726
* Assembly parsing for 2-register sequential variant of VLD2.Jim Grosbach2011-10-211-0/+14
| | | | llvm-svn: 142691
* Assembly parsing for 4-register variant of VLD1.Jim Grosbach2011-10-211-0/+12
| | | | llvm-svn: 142682
* Assembly parsing for 3-register variant of VLD1.Jim Grosbach2011-10-211-0/+12
| | | | llvm-svn: 142675
* ARM VLD parsing and encoding.Jim Grosbach2011-10-211-0/+12
| | | | | | | | | | | | Next step in the ongoing saga of NEON load/store assmebly parsing. Handle VLD1 instructions that take a two-register register list. Adjust the instruction definitions to only have the single encoded register as an operand. The super-register from the pseudo is kept as an implicit def, so passes which come after pseudo-expansion still know that the instruction defines the other subregs. llvm-svn: 142670
* Don't automatically set the "fc" bits on MSR instructions if the user didn't ↵Owen Anderson2011-10-211-3/+7
| | | | | | ask for them. This is a divergence from gas' behavior, but it is correct per the documentation and allows us to forge ahead with roundtrip testing. llvm-svn: 142669
* Nuke an #if0 that got accidentally left in.Jim Grosbach2011-10-211-31/+0
| | | | llvm-svn: 142658
* ARM VTBL (one register) assembly parsing and encoding.Jim Grosbach2011-10-181-0/+84
| | | | llvm-svn: 142441
* ARM assembly parsing and encoding for VMOV.i64.Jim Grosbach2011-10-181-0/+25
| | | | llvm-svn: 142356
* ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i32.Jim Grosbach2011-10-181-0/+59
| | | | llvm-svn: 142321
* ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i16.Jim Grosbach2011-10-171-0/+23
| | | | llvm-svn: 142303
* Tidy up.Jim Grosbach2011-10-171-1/+0
| | | | llvm-svn: 142297
* ARM NEON "vmov.i8" immediate assembly parsing and encoding.Jim Grosbach2011-10-171-1/+37
| | | | | | | | NEON immediates are "interesting". Start of the work to handle parsing them in an 'as' compatible manner. Getting the matcher to play nicely with these and the floating point immediates from VFP is an extra fun wrinkle. llvm-svn: 142293
* Removed set, but unused variables.Chad Rosier2011-10-171-2/+0
| | | | | | Patch by Joe Abbey <jabbey@arxan.com>. llvm-svn: 142223
* Thumb2 assembly parsing and encoding for LDC/STC.Jim Grosbach2011-10-121-2/+4
| | | | llvm-svn: 141811
* ARM parsing and encoding for the <option> form of LDC/STC instructions.Jim Grosbach2011-10-121-5/+66
| | | | llvm-svn: 141786
* ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions.Jim Grosbach2011-10-111-2/+24
| | | | | | | | Fill out the rest of the encoding information, update to properly mark the LDC/STC instructions as predicable while the LDC2/STC2 instructions are not, and adjust the parser accordingly. llvm-svn: 141721
* ARM parse alignment specifier for NEON load/store instructions.Jim Grosbach2011-10-111-29/+91
| | | | llvm-svn: 141682
* ARM Rename operand sub-structure 'Mem' to 'Memory' for a bit more clarity.Jim Grosbach2011-10-111-113/+113
| | | | llvm-svn: 141671
* Simplify operand Kind checks a bit.Jim Grosbach2011-10-101-20/+20
| | | | llvm-svn: 141592
* ARM NEON assembly parsing and encoding for VDUP(scalar).Jim Grosbach2011-10-071-0/+119
| | | | llvm-svn: 141446
* ARM prefix asmparser operand kind enums for readability.Jim Grosbach2011-10-071-172/+172
| | | | llvm-svn: 141438
* Improve ARM assembly parser diagnostic for unexpected tokens.Jim Grosbach2011-10-071-1/+2
| | | | | | | | | | | | | | | | | Consider: mov r8, r11 fred Previously, we issued the not very informative: x.s:6:1: error: unexpected token in argument list ^ Now we generate: x.s:5:14: error: unexpected token in argument list mov r8, r11 fred ^ llvm-svn: 141380
* Support a valid, but not very useful, encoding of CPSIE where none of the ↵Owen Anderson2011-10-051-12/+16
| | | | | | AIF bits are set. llvm-svn: 141190
* ARM assembly parsing and encoding for VMOV immediate.Jim Grosbach2011-10-031-0/+76
| | | | llvm-svn: 141046
* ARM parsing/encoding for VCMP/VCMPE.Jim Grosbach2011-10-031-0/+11
| | | | llvm-svn: 141038
* ARM assembly parsing and encoding for VMRS/FMSTAT.Jim Grosbach2011-10-031-0/+7
| | | | llvm-svn: 141025
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