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| author | Jim Grosbach <grosbach@apple.com> | 2011-11-10 16:44:55 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2011-11-10 16:44:55 +0000 |
| commit | 61db5a59f7a8d1d60c1da66b5e9a4c93ee31ed4d (patch) | |
| tree | 7b96dc1856c5348df5b2e11e39182e59501aadab /llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp | |
| parent | b538095011f89e422b1cff1bd192905e6ca94eee (diff) | |
| download | bcm5719-llvm-61db5a59f7a8d1d60c1da66b5e9a4c93ee31ed4d.tar.gz bcm5719-llvm-61db5a59f7a8d1d60c1da66b5e9a4c93ee31ed4d.zip | |
ARM assembly parsing for ASR(immediate).
Start of rdar://9704684
llvm-svn: 144293
Diffstat (limited to 'llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index cb0c97b4c63..e68ecec301a 100644 --- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -4541,6 +4541,21 @@ void ARMAsmParser:: processInstruction(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { switch (Inst.getOpcode()) { + // Handle the MOV complex aliases. + case ARM::ASRi: { + unsigned Amt = Inst.getOperand(2).getImm() + 1; + unsigned ShiftOp = ARM_AM::getSORegOpc(ARM_AM::asr, Amt); + MCInst TmpInst; + TmpInst.setOpcode(ARM::MOVsi); + TmpInst.addOperand(Inst.getOperand(0)); // Rd + TmpInst.addOperand(Inst.getOperand(1)); // Rn + TmpInst.addOperand(MCOperand::CreateImm(ShiftOp)); // Shift value and ty + TmpInst.addOperand(Inst.getOperand(3)); // CondCode + TmpInst.addOperand(Inst.getOperand(4)); + TmpInst.addOperand(Inst.getOperand(5)); // cc_out + Inst = TmpInst; + break; + } case ARM::LDMIA_UPD: // If this is a load of a single register via a 'pop', then we should use // a post-indexed LDR instruction instead, per the ARM ARM. |
