Assembly parsing for 4-register variant of VLD1.

llvm-svn: 142682

1 files changed, 12 insertions, 0 deletions

diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 1db82681699..36438dbe12d 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -925,6 +925,11 @@ public:
     return VectorList.Count == 3;
   }
 
+  bool isVecListFourD() const {
+    if (Kind != k_VectorList) return false;
+    return VectorList.Count == 4;
+  }
+
   bool isVectorIndex8() const {
     if (Kind != k_VectorIndex) return false;
     return VectorIndex.Val < 8;
@@ -1531,6 +1536,13 @@ public:
     Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
   }
 
+  void addVecListFourDOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands!");
+    // Only the first register actually goes on the instruction. The rest
+    // are implied by the opcode.
+    Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
+  }
+
   void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));