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* Some initial version of global mergerAnton Korobeynikov2010-04-071-1/+7
| | | | llvm-svn: 100641
* TargetRegistry: Fix create{AsmInfo,MCDisassembler} to return non-const objects.Daniel Dunbar2010-03-201-1/+1
| | | | llvm-svn: 99097
* remove dead code.Chris Lattner2010-02-021-24/+0
| | | | llvm-svn: 95134
* eliminate all the dead addSimpleCodeEmitter implementations.Chris Lattner2010-02-021-25/+0
| | | | | | | eliminate random "code emitter" stuff in Alpha, except for the JIT path. Next up, remove the template cruft. llvm-svn: 95131
* For aligned load/store instructions, it's only required to know whether aJim Grosbach2010-01-191-4/+0
| | | | | | | | | | | function can support dynamic stack realignment. That's a much easier question to answer at instruction selection stage than whether the function actually will have dynamic alignment prologue. This allows the removal of the stack alignment heuristic pass, and improves code quality for cases where the heuristic would result in dynamic alignment code being generated when it was not strictly necessary. llvm-svn: 93885
* Factor the stack alignment calculations out into a target independent pass.Jim Grosbach2009-12-021-1/+1
| | | | | | No functionality change. llvm-svn: 90336
* Detect need for autoalignment of the stack earlier to catch spills moreJim Grosbach2009-11-151-0/+4
| | | | | | | conservatively. eliminateFrameIndex() machinery adjust to handle addr mode 6 (vld1/vst1) used for spills. Fix tests to expect aligned Q-reg spilling llvm-svn: 88874
* indicate what the native integer types for the target are.Chris Lattner2009-11-071-4/+4
| | | | | | Please verify. llvm-svn: 86397
* - Add pseudo instructions tLDRpci_pic and t2LDRpci_pic which does a pc-relativeEvan Cheng2009-11-061-0/+4
| | | | | | | | | | | | load of a GV from constantpool and then add pc. It allows the code sequence to be rematerializable so it would be hoisted by machine licm. - Add a late pass to break these pseudo instructions into a number of real instructions. Also move the code in Thumb2 IT pass that breaks up t2MOVi32imm to this pass. This is done before post regalloc scheduling to allow the scheduler to proper schedule these instructions. It also allow them to be if-converted and shrunk by later passes. llvm-svn: 86304
* Pass StringRef by value.Daniel Dunbar2009-11-061-2/+1
| | | | llvm-svn: 86251
* Move subtarget check upper for NEON reg-reg fixup pass.Anton Korobeynikov2009-11-031-1/+2
| | | | llvm-svn: 85914
* Turn neon reg-reg moves fixup code into separate pass. This should reduce ↵Anton Korobeynikov2009-11-031-2/+5
| | | | | | the compile time. llvm-svn: 85850
* Revert r85346 change to control tail merging by CodeGenOpt::Level.Bob Wilson2009-10-281-1/+1
| | | | | | I'm going to redo this using the OptimizeForSize function attribute. llvm-svn: 85426
* Record CodeGen optimization level in the BranchFolding pass so that we canBob Wilson2009-10-271-1/+1
| | | | | | | | | | | | | | | | use it to control tail merging when there is a tradeoff between performance and code size. When there is only 1 instruction in the common tail, we have been merging. That can be good for code size but is a definite loss for performance. Now we will avoid tail merging in that case when the optimization level is "Aggressive", i.e., "-O3". Radar 7338114. Since the IfConversion pass invokes BranchFolding, it too needs to know the optimization level. Note that I removed the RegisterPass instantiation for IfConversion because it required a default constructor. If someone wants to keep that for some reason, we can add a default constructor with a hard-wired optimization level. llvm-svn: 85346
* Revert 84843. Evan, this was breaking some of the if-conversion tests.Bob Wilson2009-10-221-3/+5
| | | | llvm-svn: 84868
* Move if-conversion before post-regalloc scheduling so the predicated ↵Evan Cheng2009-10-221-5/+3
| | | | | | instruction get scheduled properly. llvm-svn: 84843
* Trim include.Evan Cheng2009-10-221-1/+0
| | | | llvm-svn: 84831
* Move load / store multiple before post-alloc scheduling.Evan Cheng2009-10-021-10/+2
| | | | llvm-svn: 83236
* Add a option which would move ld/st multiple pass before post-alloc scheduling.Evan Cheng2009-09-301-1/+16
| | | | llvm-svn: 83145
* Pass the optimization level when constructing the ARM instruction selector.Bob Wilson2009-09-281-1/+1
| | | | | | | Otherwise, it is always set to "default", which prevents debug info from even being generated during isel. Radar 7250345. llvm-svn: 82988
* Enable pre-regalloc load / store multiple pass for Thumb2.Evan Cheng2009-09-271-6/+5
| | | | llvm-svn: 82893
* Really remove this option.Evan Cheng2009-09-261-3/+0
| | | | llvm-svn: 82838
* Remove a couple of unused command line options.Evan Cheng2009-09-261-7/+3
| | | | llvm-svn: 82837
* trivial whitespace cleanupJim Grosbach2009-09-141-2/+2
| | | | llvm-svn: 81773
* rename COFFMCAsmInfo -> MCAsmInfoCOFF, likewise for darwin.Chris Lattner2009-08-221-1/+1
| | | | llvm-svn: 79773
* Rename TargetAsmInfo (and its subclasses) to MCAsmInfo.Chris Lattner2009-08-221-6/+6
| | | | llvm-svn: 79763
* Turn on if-conversion for thumb2.Evan Cheng2009-08-151-6/+4
| | | | llvm-svn: 79084
* Revert 78892 and 78895, these break generating working executables onDaniel Dunbar2009-08-131-1/+1
| | | | | | | | | | | | | | | | | | | | | x86_64-apple-darwin10. --- Reverse-merging r78895 into '.': U test/CodeGen/PowerPC/2008-12-12-EH.ll U lib/Target/DarwinTargetAsmInfo.cpp --- Reverse-merging r78892 into '.': U include/llvm/Target/DarwinTargetAsmInfo.h U lib/Target/X86/X86TargetAsmInfo.cpp U lib/Target/X86/X86TargetAsmInfo.h U lib/Target/ARM/ARMTargetAsmInfo.h U lib/Target/ARM/ARMTargetMachine.cpp U lib/Target/ARM/ARMTargetAsmInfo.cpp U lib/Target/PowerPC/PPCTargetAsmInfo.cpp U lib/Target/PowerPC/PPCTargetAsmInfo.h U lib/Target/PowerPC/PPCTargetMachine.cpp G lib/Target/DarwinTargetAsmInfo.cpp llvm-svn: 78919
* fix a minor fixme. When building with SL and later tools, the ".eh" symbolsChris Lattner2009-08-131-1/+1
| | | | | | don't need to be exported from the .o files. llvm-svn: 78892
* Change TargetAsmInfo to be constructed via TargetRegistry from a Target+TripleChris Lattner2009-08-121-10/+16
| | | | | | | | pair instead of from a virtual method on TargetMachine. This cuts the final ties of TargetAsmInfo to TargetMachine, meaning that MC can now use TargetAsmInfo. llvm-svn: 78802
* pass the TargetTriple down from each target ctor to theChris Lattner2009-08-111-1/+1
| | | | | | LLVMTargetMachine ctor. It is currently unused. llvm-svn: 78711
* Whitespace cleanup. Remove trailing whitespace.Jim Grosbach2009-08-111-1/+1
| | | | llvm-svn: 78666
* Adding a blank line back.Evan Cheng2009-08-111-0/+1
| | | | llvm-svn: 78654
* Enable Thumb2 instruction shrinking (32-bit to 16-bit) pass. Convert a bunch ↵Evan Cheng2009-08-101-5/+1
| | | | | | of thumb2 tests to FileCheck. llvm-svn: 78622
* Add a skeleton Thumb2 instruction size reduction pass.Evan Cheng2009-08-081-1/+6
| | | | llvm-svn: 78456
* Add a new pre-allocation pass to assign adjacent registers for Neon instructionsBob Wilson2009-08-051-0/+3
| | | | | | | | | that have that constraint. This is currently just assigning a fixed set of registers, and it only handles VLDn for n=2,3,4 with DPR registers. I'm going to expand it to handle more operations next; we can make it smarter once everything is working correctly. llvm-svn: 78256
* Oops. I didn't mean to commit this piece yet.Bob Wilson2009-08-051-2/+0
| | | | llvm-svn: 78146
* Change DAG nodes for Neon VLD2/3/4 operations to return multiple results.Bob Wilson2009-08-051-0/+2
| | | | | | | | | Get rid of yesterday's code to fix the register usage during isel. Select the new DAG nodes to machine instructions. The new pre-alloc pass to choose adjacent registers for these results is not done, so the results of this will generally not assemble yet. llvm-svn: 78136
* Enable load / store multiple pass for Thumb2. It's not using ldrd / strd yet.Evan Cheng2009-08-041-2/+3
| | | | llvm-svn: 78104
* Move most targets TargetMachine constructor to only taking a target triple.Daniel Dunbar2009-08-021-7/+6
| | | | | | - The C, C++, MSIL, and Mips backends still need the module. llvm-svn: 77927
* Normalize Subtarget constructors to take a target triple string instead ofDaniel Dunbar2009-08-021-1/+1
| | | | | | | | | | Module*. Also, dropped uses of TargetMachine where unnecessary. The only target which still takes a TargetMachine& is Mips, I would appreciate it if someone would normalize this to match other targets. llvm-svn: 77918
* ARM TAI no longer needs a TM, but createTargetAsmInfo() still does.Chris Lattner2009-08-021-2/+2
| | | | llvm-svn: 77878
* remove dead code.Chris Lattner2009-07-271-4/+3
| | | | llvm-svn: 77233
* Add new helpers for registering targets.Daniel Dunbar2009-07-251-9/+6
| | | | | | - Less boilerplate == good. llvm-svn: 77052
* Put Target definitions inside Target specific header, and llvm namespace.Daniel Dunbar2009-07-181-4/+3
| | | | llvm-svn: 76344
* Kill off <TARGET>MachineModule variables, and <TARGETASMPRINTER>ForceLinkDaniel Dunbar2009-07-161-7/+0
| | | | | | | variables. - Module initialization functions supplanted the need for these. llvm-svn: 75886
* Lift addAssemblyEmitter into LLVMTargetMachine.Daniel Dunbar2009-07-151-12/+0
| | | | | | - No functionality change. llvm-svn: 75859
* Lift DumpAsm / -print-emitted-asm functionality into LLVMTargetMachine.Daniel Dunbar2009-07-151-24/+0
| | | | | | - No intended functionality change. llvm-svn: 75848
* Remove old style hacks to register AsmPrinter into TargetMachine.Daniel Dunbar2009-07-151-8/+4
| | | | | | - No intended functionality change. llvm-svn: 75843
* Reapply TargetRegistry refactoring commits.Daniel Dunbar2009-07-151-63/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | --- Reverse-merging r75799 into '.': U test/Analysis/PointerTracking U include/llvm/Target/TargetMachineRegistry.h U include/llvm/Target/TargetMachine.h U include/llvm/Target/TargetRegistry.h U include/llvm/Target/TargetSelect.h U tools/lto/LTOCodeGenerator.cpp U tools/lto/LTOModule.cpp U tools/llc/llc.cpp U lib/Target/PowerPC/PPCTargetMachine.h U lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp U lib/Target/PowerPC/PPCTargetMachine.cpp U lib/Target/PowerPC/PPC.h U lib/Target/ARM/ARMTargetMachine.cpp U lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp U lib/Target/ARM/ARMTargetMachine.h U lib/Target/ARM/ARM.h U lib/Target/XCore/XCoreTargetMachine.cpp U lib/Target/XCore/XCoreTargetMachine.h U lib/Target/PIC16/PIC16TargetMachine.cpp U lib/Target/PIC16/PIC16TargetMachine.h U lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp U lib/Target/Alpha/AlphaTargetMachine.cpp U lib/Target/Alpha/AlphaTargetMachine.h U lib/Target/X86/X86TargetMachine.h U lib/Target/X86/X86.h U lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h U lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp U lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h U lib/Target/X86/X86TargetMachine.cpp U lib/Target/MSP430/MSP430TargetMachine.cpp U lib/Target/MSP430/MSP430TargetMachine.h U lib/Target/CppBackend/CPPTargetMachine.h U lib/Target/CppBackend/CPPBackend.cpp U lib/Target/CBackend/CTargetMachine.h U lib/Target/CBackend/CBackend.cpp U lib/Target/TargetMachine.cpp U lib/Target/IA64/IA64TargetMachine.cpp U lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp U lib/Target/IA64/IA64TargetMachine.h U lib/Target/IA64/IA64.h U lib/Target/MSIL/MSILWriter.cpp U lib/Target/CellSPU/SPUTargetMachine.h U lib/Target/CellSPU/SPU.h U lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp U lib/Target/CellSPU/SPUTargetMachine.cpp U lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp U lib/Target/Mips/MipsTargetMachine.cpp U lib/Target/Mips/MipsTargetMachine.h U lib/Target/Mips/Mips.h U lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp U lib/Target/Sparc/SparcTargetMachine.cpp U lib/Target/Sparc/SparcTargetMachine.h U lib/ExecutionEngine/JIT/TargetSelect.cpp U lib/Support/TargetRegistry.cpp llvm-svn: 75820
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