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path: root/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp
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* Teach ARM Target to use the tblgen support for generating an MC'izedJim Grosbach2010-11-031-46/+62
| | | | | | CodeEmitter. llvm-svn: 118209
* trailing whitespaceJim Grosbach2010-11-031-2/+2
| | | | llvm-svn: 118199
* Put the PC encoding in the correct bit position.Bill Wendling2010-11-031-1/+1
| | | | llvm-svn: 118151
* The MC code couldn't handle ARM LDR instructions with negative offsets:Bill Wendling2010-11-031-19/+65
| | | | | | | | | | | | vldr.64 d1, [r0, #-32] The problem was with how the addressing mode 5 encodes the offsets. This change makes sure that the way offsets are handled in addressing mode 5 is consistent throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue" method into an "Imm12" and "addressing mode 5" version. But not to worry! The majority of the duplicated code has been unified. llvm-svn: 118144
* Obsessive formatting changes. No functionality impact.Bill Wendling2010-11-021-31/+37
| | | | llvm-svn: 118103
* Omit unused parameter name.Bill Wendling2010-11-021-1/+1
| | | | llvm-svn: 118099
* Simplify the EncodeInstruction method now that a lot of the special case stuffBill Wendling2010-11-021-13/+6
| | | | | | is handled with the MC encoder. llvm-svn: 118098
* Rename getAddrModeImm12OpValue to getAddrModeImmOpValue and expand it to workBill Wendling2010-11-021-21/+20
| | | | | | | | with immediates up to 16-bits in size. The same logic is applied to other LDR encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in VLDR's case). Removing the "12" allows it to be more generic. llvm-svn: 118094
* Rename encoder methods to match naming convention.Owen Anderson2010-11-021-4/+4
| | | | llvm-svn: 118093
* Add correct encodings for the rest of the vld instructions that we generate.Owen Anderson2010-11-021-1/+1
| | | | llvm-svn: 118053
* Add correct NEON encodings for vld2, vld3, and vld4 basic variants.Owen Anderson2010-11-021-0/+9
| | | | llvm-svn: 117997
* Add aesthetic break.Owen Anderson2010-11-021-1/+1
| | | | llvm-svn: 117986
* Add correct NEON encodings for the "multiple single elements" form of vld.Owen Anderson2010-11-021-1/+17
| | | | llvm-svn: 117984
* Explicitly check for non-consant reference in an LDRi12 instruction. Add FIXMEJim Grosbach2010-11-011-1/+10
| | | | | | for handling the fixup necessary. llvm-svn: 117978
* Remove unused function.Jim Grosbach2010-11-011-13/+0
| | | | llvm-svn: 117977
* Avoid re-evaluating MI.getNumOperands() every iteration of the loop.Jim Grosbach2010-10-301-1/+1
| | | | llvm-svn: 117766
* Encode the register list operands for ARM mode LDM/STM instructions.Jim Grosbach2010-10-301-0/+15
| | | | llvm-svn: 117753
* trailing whitespaceJim Grosbach2010-10-291-2/+2
| | | | llvm-svn: 117740
* s/getNEONVcvtImm32/getNEONVcvtImm32OpValue/ to be consistent with other operandJim Grosbach2010-10-291-1/+1
| | | | | | encoder functions. llvm-svn: 117738
* PLD, PLDW, PLI encodings, plus refactor their use of addrmode2.Jim Grosbach2010-10-281-3/+9
| | | | llvm-svn: 117571
* Provide correct encodings for NEON vcvt, which has its own special immediate ↵Owen Anderson2010-10-271-0/+4
| | | | | | | | encoding for specifying fractional bits for fixed point conversions. llvm-svn: 117501
* First part of refactoring ARM addrmode2 (load/store) instructions to be moreJim Grosbach2010-10-261-0/+23
| | | | | | | | explicit about the operands. Split out the different variants into separate instructions. This gives us the ability to, among other things, assign different scheduling itineraries to the variants. rdar://8477752. llvm-svn: 117409
* ARM Binary encoding information for BFC/BFI instructions.Jim Grosbach2010-10-211-0/+14
| | | | llvm-svn: 117072
* Move the encoding logic for Q registers into getMachineOpValue().Owen Anderson2010-10-211-1/+12
| | | | llvm-svn: 117060
* ARM mode encoding information for UBFX and SBFX instructions.Jim Grosbach2010-10-151-0/+4
| | | | llvm-svn: 116588
* Add support for vmov.f64/.f32 encoding. There's a bit of a hack going onBill Wendling2010-10-141-3/+5
| | | | | | | | | here. The f32 in FCONSTS is handled as a double instead of a float in the code. So the encoding of the immediate into the instruction isn't exactly in line with the documentation in that regard. But given that we know it's handled as a double, it doesn't cause any harm. llvm-svn: 116471
* Add ARM mode encoding for [SU]XT[BH] and [SU]XTA[BH] instructions.Jim Grosbach2010-10-131-0/+10
| | | | llvm-svn: 116421
* Add the rest of the ARM so_reg encoding options (register shifted register)Jim Grosbach2010-10-121-18/+74
| | | | | | | and move to a custom operand encoder. Remove the last of the special handling stuff from ARMMCCodeEmitter::EncodeInstruction. llvm-svn: 116377
* Move the ARM so_imm encoding into a custom operand encoder and remove theJim Grosbach2010-10-121-26/+14
| | | | | | | explicit handling of the instructions referencing it from the MC code emitter. llvm-svn: 116367
* Add custom encoder for the 's' bit denoting whether an ARM arithmeticJim Grosbach2010-10-121-9/+7
| | | | | | | instruction should set the processor status flags or not. Remove the now unnecessary special handling for the bit from the MCCodeEmitter. llvm-svn: 116360
* Add MOVi ARM encoding.Jim Grosbach2010-10-121-0/+7
| | | | llvm-svn: 116321
* Nuke unused wrapper function.Jim Grosbach2010-10-121-3/+0
| | | | llvm-svn: 116318
* Add encoding information for the remainder of the generic arithmeticJim Grosbach2010-10-121-19/+36
| | | | | | ARM instructions. llvm-svn: 116313
* MC machine encoding for simple aritmetic instructions that use a shiftedJim Grosbach2010-10-111-1/+21
| | | | | | register operand. llvm-svn: 116259
* Implement a few more binary encoding bits. Still very early stage proof-of-Jim Grosbach2010-10-081-0/+19
| | | | | | | | | | concept level stuff at this point, but it is generally working for those instructions that know how to map the operands. This patch fills in the register operands for add/sub/or/etc instructions and adds the conditional execution predicate encoding. llvm-svn: 116112
* Reapply 116059, this time without the fatfingered pasto at the top.Jim Grosbach2010-10-081-9/+5
| | | | | | ''const'ify getMachineOpValue() and associated helpers.' llvm-svn: 116067
* Reverting 116059. Bots are unhappy with it.Jim Grosbach2010-10-081-5/+9
| | | | llvm-svn: 116064
* 'const'ify getMachineOpValue() and associated helpers.Jim Grosbach2010-10-081-9/+5
| | | | llvm-svn: 116059
* Enable binary encoding of some simple instructions.Jim Grosbach2010-10-081-0/+8
| | | | llvm-svn: 116022
* Make <target>CodeEmitter::getBinaryCodeForInstr() a const method.Jim Grosbach2010-10-081-1/+1
| | | | llvm-svn: 116018
* Trivial MC code emitter shell. No instruction forms actually handled yet.Jim Grosbach2010-10-071-3/+19
| | | | llvm-svn: 115993
* Include the auto-generated bits for machine encoding.Jim Grosbach2010-10-071-0/+20
| | | | llvm-svn: 115987
* ARM instruction don't have instruction prefixes, so remove the helper functionsJim Grosbach2010-10-071-16/+1
| | | | | | for them from the MCCodeEmitter. llvm-svn: 115975
* Fix build.Michael J. Spencer2010-09-181-0/+1
| | | | llvm-svn: 114292
* Add skeleton infrastructure for the ARMMCCodeEmitter class. Patch by Jason Kim!Jim Grosbach2010-09-171-0/+114
llvm-svn: 114195
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