| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | First stab at providing correct Thumb2 encodings, start with adc. | Owen Anderson | 2010-11-12 | 1 | -0/+52 |
| * | Start of support for binary emit of 16-it Thumb instructions. | Jim Grosbach | 2010-11-11 | 1 | -3/+10 |
| * | Fill out support for Thumb2 encodings of NEON instructions. | Owen Anderson | 2010-11-11 | 1 | -0/+17 |
| * | Add correct Thumb2 encodings for NEON vst[1,2,3,4] and vld[1,2,3,4]. | Owen Anderson | 2010-11-11 | 1 | -1/+18 |
| * | Add support for Thumb2 encodings of NEON data processing instructions, using ... | Owen Anderson | 2010-11-11 | 1 | -0/+23 |
| * | Encoding of destination fixup for ARM branch and conditional branch | Jim Grosbach | 2010-11-11 | 1 | -3/+28 |
| * | Encoding for ARM LDRSH_POST. | Jim Grosbach | 2010-11-11 | 1 | -0/+23 |
| * | ARM STRH encoding information. | Jim Grosbach | 2010-11-11 | 1 | -1/+26 |
| * | ARM LDM encoding for the mode (ia, ib, da, db) operand. | Jim Grosbach | 2010-11-10 | 1 | -0/+13 |
| * | For ARM load/store instructions, encode [reg+reg] with no shifter immediate as | Jim Grosbach | 2010-11-09 | 1 | -0/+3 |
| * | Add encoder method for ARM load/store shifted register offset operands. | Jim Grosbach | 2010-11-09 | 1 | -0/+45 |
| * | Add support for a few simple fixups to the ARM Darwin asm backend. This allows | Jim Grosbach | 2010-11-09 | 1 | -8/+2 |
| * | Revert r118457 and r118458. These won't hold for GPRs. | Bill Wendling | 2010-11-09 | 1 | -5/+8 |
| * | Get the register and count from the register list operands. | Bill Wendling | 2010-11-08 | 1 | -8/+5 |
| * | Add ARM fixup info for load/store label references. Probably will need a bit of | Jim Grosbach | 2010-11-04 | 1 | -30/+51 |
| * | Teach ARM Target to use the tblgen support for generating an MC'ized | Jim Grosbach | 2010-11-03 | 1 | -46/+62 |
| * | trailing whitespace | Jim Grosbach | 2010-11-03 | 1 | -2/+2 |
| * | Put the PC encoding in the correct bit position. | Bill Wendling | 2010-11-03 | 1 | -1/+1 |
| * | The MC code couldn't handle ARM LDR instructions with negative offsets: | Bill Wendling | 2010-11-03 | 1 | -19/+65 |
| * | Obsessive formatting changes. No functionality impact. | Bill Wendling | 2010-11-02 | 1 | -31/+37 |
| * | Omit unused parameter name. | Bill Wendling | 2010-11-02 | 1 | -1/+1 |
| * | Simplify the EncodeInstruction method now that a lot of the special case stuff | Bill Wendling | 2010-11-02 | 1 | -13/+6 |
| * | Rename getAddrModeImm12OpValue to getAddrModeImmOpValue and expand it to work | Bill Wendling | 2010-11-02 | 1 | -21/+20 |
| * | Rename encoder methods to match naming convention. | Owen Anderson | 2010-11-02 | 1 | -4/+4 |
| * | Add correct encodings for the rest of the vld instructions that we generate. | Owen Anderson | 2010-11-02 | 1 | -1/+1 |
| * | Add correct NEON encodings for vld2, vld3, and vld4 basic variants. | Owen Anderson | 2010-11-02 | 1 | -0/+9 |
| * | Add aesthetic break. | Owen Anderson | 2010-11-02 | 1 | -1/+1 |
| * | Add correct NEON encodings for the "multiple single elements" form of vld. | Owen Anderson | 2010-11-02 | 1 | -1/+17 |
| * | Explicitly check for non-consant reference in an LDRi12 instruction. Add FIXME | Jim Grosbach | 2010-11-01 | 1 | -1/+10 |
| * | Remove unused function. | Jim Grosbach | 2010-11-01 | 1 | -13/+0 |
| * | Avoid re-evaluating MI.getNumOperands() every iteration of the loop. | Jim Grosbach | 2010-10-30 | 1 | -1/+1 |
| * | Encode the register list operands for ARM mode LDM/STM instructions. | Jim Grosbach | 2010-10-30 | 1 | -0/+15 |
| * | trailing whitespace | Jim Grosbach | 2010-10-29 | 1 | -2/+2 |
| * | s/getNEONVcvtImm32/getNEONVcvtImm32OpValue/ to be consistent with other operand | Jim Grosbach | 2010-10-29 | 1 | -1/+1 |
| * | PLD, PLDW, PLI encodings, plus refactor their use of addrmode2. | Jim Grosbach | 2010-10-28 | 1 | -3/+9 |
| * | Provide correct encodings for NEON vcvt, which has its own special immediate ... | Owen Anderson | 2010-10-27 | 1 | -0/+4 |
| * | First part of refactoring ARM addrmode2 (load/store) instructions to be more | Jim Grosbach | 2010-10-26 | 1 | -0/+23 |
| * | ARM Binary encoding information for BFC/BFI instructions. | Jim Grosbach | 2010-10-21 | 1 | -0/+14 |
| * | Move the encoding logic for Q registers into getMachineOpValue(). | Owen Anderson | 2010-10-21 | 1 | -1/+12 |
| * | ARM mode encoding information for UBFX and SBFX instructions. | Jim Grosbach | 2010-10-15 | 1 | -0/+4 |
| * | Add support for vmov.f64/.f32 encoding. There's a bit of a hack going on | Bill Wendling | 2010-10-14 | 1 | -3/+5 |
| * | Add ARM mode encoding for [SU]XT[BH] and [SU]XTA[BH] instructions. | Jim Grosbach | 2010-10-13 | 1 | -0/+10 |
| * | Add the rest of the ARM so_reg encoding options (register shifted register) | Jim Grosbach | 2010-10-12 | 1 | -18/+74 |
| * | Move the ARM so_imm encoding into a custom operand encoder and remove the | Jim Grosbach | 2010-10-12 | 1 | -26/+14 |
| * | Add custom encoder for the 's' bit denoting whether an ARM arithmetic | Jim Grosbach | 2010-10-12 | 1 | -9/+7 |
| * | Add MOVi ARM encoding. | Jim Grosbach | 2010-10-12 | 1 | -0/+7 |
| * | Nuke unused wrapper function. | Jim Grosbach | 2010-10-12 | 1 | -3/+0 |
| * | Add encoding information for the remainder of the generic arithmetic | Jim Grosbach | 2010-10-12 | 1 | -19/+36 |
| * | MC machine encoding for simple aritmetic instructions that use a shifted | Jim Grosbach | 2010-10-11 | 1 | -1/+21 |
| * | Implement a few more binary encoding bits. Still very early stage proof-of- | Jim Grosbach | 2010-10-08 | 1 | -0/+19 |
