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path: root/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
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* Clean up some code for clarity.Bob Wilson2011-04-051-5/+24
| | | | llvm-svn: 128953
* Check early if this is an unsupported opcode, so that we can avoid ↵Owen Anderson2011-03-291-0/+4
| | | | | | needlessly instantiating the base register in some cases. llvm-svn: 128481
* Add safety check that didn't show up in testing.Owen Anderson2011-03-291-0/+1
| | | | llvm-svn: 128467
* Get rid of the non-writeback versions VLDMDB and VSTMDB, which don't ↵Owen Anderson2011-03-291-17/+5
| | | | | | actually exist. llvm-svn: 128461
* Do not form thumb2 ldrd / strd if the offset is by multiple of 4. rdar://9133587Evan Cheng2011-03-151-9/+3
| | | | llvm-svn: 127683
* Teach ARMLoadStoreOptimizer to remove kill flags from merged instructions as ↵Jakob Stoklund Olesen2011-02-151-21/+15
| | | | | | | | | | | | | | | | | | | | | | | | | well. This is necessary to avoid a crash in certain tangled situations where a kill flag is first correctly moved to a merged instruction, and then needs to be moved again: STR %R0, a... STR %R0<kill>, b... First becomes: STR %R0, b... STM a, %R0<kill>, ... and then: STM a, %R0, ... STM b, %R0<kill>, ... We can now remove the kill flag from the merged STM when needed. 8960050. llvm-svn: 125591
* Move code for OffsetCompare struct closer to where it is used.Bob Wilson2011-02-071-11/+11
| | | | llvm-svn: 125009
* Fix a few more places that should use MBB::getLastNonDebugInstr().Jakob Stoklund Olesen2011-01-131-1/+1
| | | | llvm-svn: 123408
* Do not model all INLINEASM instructions as having unmodelled side effects.Evan Cheng2011-01-071-1/+1
| | | | | | | | | | Instead encode llvm IR level property "HasSideEffects" in an operand (shared with IsAlignStack). Added MachineInstrs::hasUnmodeledSideEffects() to check the operand when the instruction is an INLINEASM. This allows memory instructions to be moved around INLINEASM instructions. llvm-svn: 123044
* PR8921: LDM/POP do not support interworking prior to v5t.Bob Wilson2011-01-061-1/+2
| | | | llvm-svn: 122970
* Missed the _RET versions of LDMIA.Bill Wendling2010-11-181-0/+2
| | | | llvm-svn: 119726
* Add missing opcodes now that this function's used in more than one place.Bill Wendling2010-11-171-0/+20
| | | | llvm-svn: 119539
* Revert r119109 for now. It's breaking 176.gcc.Evan Cheng2010-11-171-17/+0
| | | | llvm-svn: 119492
* The machine instruction no longer encodes the submode as a separate operand. WeBill Wendling2010-11-171-2/+8
| | | | | | should get the submode from the load/store multiple instruction's opcode. llvm-svn: 119461
* Encode the multi-load/store instructions with their respective modes ('ia',Bill Wendling2010-11-161-67/+236
| | | | | | | | | 'db', 'ib', 'da') instead of having that mode as a separate field in the instruction. It's more convenient for the asm parser and much more readable for humans. <rdar://problem/8654088> llvm-svn: 119310
* Make sure ARM multi load / store pass copies memoperands when forming ldrd / ↵Evan Cheng2010-11-151-0/+17
| | | | | | strd. pr8113. llvm-svn: 119109
* Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, likeJim Grosbach2010-10-271-69/+34
| | | | | | | | the LDR instructions have. This makes the literal/register forms of the instructions explicit and allows us to assign scheduling itineraries appropriately. rdar://8477752 llvm-svn: 117505
* One more spot where the new arm mode LDR instruction representationJim Grosbach2010-10-271-3/+3
| | | | | | | doesn't need the additional addrmode2 register operand. Missed it the first time around. llvm-svn: 117421
* First part of refactoring ARM addrmode2 (load/store) instructions to be moreJim Grosbach2010-10-261-18/+27
| | | | | | | | explicit about the operands. Split out the different variants into separate instructions. This gives us the ability to, among other things, assign different scheduling itineraries to the variants. rdar://8477752. llvm-svn: 117409
* Grammar.Jim Grosbach2010-10-261-1/+1
| | | | llvm-svn: 117388
* Transfer implicit ops when forming load multiple and return instructions.Evan Cheng2010-10-221-0/+1
| | | | llvm-svn: 117151
* Increase ARM APCS preferred alignment for i64 and f64 from 32 bits to 64 bits.Bob Wilson2010-09-291-1/+1
| | | | | | | LDM/STM instructions can run one cycle faster on some ARM processors if the memory address is 64-bit aligned. Radar 8489376. llvm-svn: 115047
* move getRegisterNumbering() to out of ARMBaseRegisterInfo into the helperJim Grosbach2010-09-151-2/+2
| | | | | | | | | functions in ARMBaseInfo.h so it can be used in the MC library as well. For anything bigger than this, we may want a means to have a small support library for shared helper functions like this. Cross that bridge when we come to it. llvm-svn: 114016
* Calculate the number of VLDM/VSTM registers by subtracting the number ofBob Wilson2010-09-101-2/+2
| | | | | | fixed operands from the total number of operands (including the variadic ones). llvm-svn: 113597
* Fix merging base-updates for VLDM/VSTM: Before I switched these instructionsBob Wilson2010-09-101-1/+2
| | | | | | | | | | to use AddrMode4, there was a count of the registers stored in one of the operands. I changed that to just count the operands but forgot to adjust for the size of D registers. This was noticed by Evan as a performance problem but it is a potential correctness bug as well, since it is possible that this could merge a base update with a non-matching immediate. llvm-svn: 113576
* Remember to clear the shadow kill flag at the same time as clearing the realJakob Stoklund Olesen2010-08-301-0/+1
| | | | | | | | | | | kill flag. This could cause duplicate kill flags when the same register was used twice in a continuous sequence of STRs. There is no small test case. <rdar://problem/8218046> llvm-svn: 112534
* When merging Thumb2 loads/stores, do not give up when the offset is one ofBob Wilson2010-08-271-10/+7
| | | | | | | | the special values that for ARM would be used with IB or DA modes. Fall through and consider materializing a new base address is it would be profitable. llvm-svn: 112329
* Change ARM VFP VLDM/VSTM instructions to use addressing mode #4, just likeBob Wilson2010-08-271-77/+41
| | | | | | | | | | | | | | | | | | | all the other LDM/STM instructions. This fixes asm printer crashes when compiling with -O0. I've changed one of the NEON tests (vst3.ll) to run with -O0 to check this in the future. Prior to this change VLDM/VSTM used addressing mode #5, but not really. The offset field was used to hold a count of the number of registers being loaded or stored, and the AM5 opcode field was expanded to specify the IA or DB mode, instead of the standard ADD/SUB specifier. Much of the backend was not aware of these special cases. The crashes occured when rewriting a frameindex caused the AM5 offset field to be changed so that it did not have a valid submode. I don't know exactly what changed to expose this now. Maybe we've never done much with -O0 and NEON. Regardless, there's no longer any reason to keep a count of the VLDM/VSTM registers, so we can use addressing mode #4 and clean things up in a lot of places. llvm-svn: 112322
* Unsigned value cannot be < 0.Bob Wilson2010-08-271-2/+2
| | | | llvm-svn: 112300
* Reapply r110396, with fixes to appease the Linux buildbot gods.Owen Anderson2010-08-061-2/+2
| | | | llvm-svn: 110460
* Revert r110396 to fix buildbots.Owen Anderson2010-08-061-2/+2
| | | | llvm-svn: 110410
* Don't use PassInfo* as a type identifier for passes. Instead, use the ↵Owen Anderson2010-08-051-2/+2
| | | | | | | | address of the static ID member as the sole unique type identifier. Clean up APIs related to this change. llvm-svn: 110396
* When no memoperands are present, assume unaligned, volatile.Jakob Stoklund Olesen2010-06-291-10/+13
| | | | llvm-svn: 107114
* Use pre-increment instead of post-increment when the result is not used.Dan Gohman2010-06-221-12/+12
| | | | llvm-svn: 106542
* Fix PR7421: bug in kill transferring logic. It was ignoring loads / stores ↵Evan Cheng2010-06-211-39/+66
| | | | | | which have already been processed. llvm-svn: 106481
* Make sure to skip dbg_value instructions when finding an insertion point forJim Grosbach2010-06-151-1/+2
| | | | | | the combined load/store instruction. rdar://7797940 llvm-svn: 105982
* be slightly more subtle about skipping dbg_value instructions; otherwise, if aJim Grosbach2010-06-091-5/+6
| | | | | | | | dbg_value immediately follows a sequence of ldr/str instructions that should be combined into an ldm/stm and is the last instruction in the block, then combine may end up being skipped. llvm-svn: 105758
* fix copy/paste/modify think-oJim Grosbach2010-06-081-1/+1
| | | | llvm-svn: 105653
* Another fix to prevent debug info from affecting codegen. rdar://7797940Jim Grosbach2010-06-041-0/+4
| | | | llvm-svn: 105470
* more dbg_value adjustments so debug info doesn't affect codegenJim Grosbach2010-06-041-2/+4
| | | | llvm-svn: 105454
* fix typoJim Grosbach2010-06-041-1/+1
| | | | llvm-svn: 105441
* Teach the ARM load-store optimizer to deal with dbg_value instructions.Jim Grosbach2010-06-031-4/+16
| | | | llvm-svn: 105427
* Clean up 80 column violations. No functional change.Jim Grosbach2010-06-021-2/+2
| | | | llvm-svn: 105350
* Add more const qualifiers for LLVM IR pointers in CodeGen.Dan Gohman2010-04-151-1/+1
| | | | llvm-svn: 101342
* vldm/vstm can only do up to 16 double-word registers at a time.Jim Grosbach2010-03-261-1/+5
| | | | | | Radar 7797856 llvm-svn: 99630
* pr6652: Use LDM to restore PC to the return address on ARMv4.Bob Wilson2010-03-201-6/+11
| | | | | | Patch by John Tytgat! llvm-svn: 99096
* Remove redundant writeback flag in ARM addressing mode 5.Bob Wilson2010-03-161-4/+3
| | | | llvm-svn: 98648
* Remove the writeback flag from ARM's address mode 4. Now that we have separateBob Wilson2010-03-161-2/+1
| | | | | | instructions for ld/st with writeback, the flag is completely redundant. llvm-svn: 98643
* Wrap a long line and add some parens to be consistent.Bob Wilson2010-03-161-2/+3
| | | | llvm-svn: 98596
* Change ARM ld/st multiple instructions to have variant instructions forBob Wilson2010-03-131-84/+99
| | | | | | | | | | | | | | | writebacks to the address register. This gets rid of the hack that the first register on the list was the magic writeback register operand. There was an implicit constraint that if that operand was not reg0 it had to match the base register operand. The post-RA scheduler's antidependency breaker did not understand that constraint and sometimes changed one without the other. This also fixes Radar 7495976 and should help the verifier work better for ARM code. There are now new ld/st instructions explicit writeback operands and explicit constraints that tie those registers together. llvm-svn: 98409
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