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path: root/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
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* Improve handling of stack accesses in Thumb-1Renato Golin2015-02-251-9/+27
| | | | | | | | | | | | | | | | | Thumb-1 only allows SP-based LDR and STR to be word-sized, and SP-base LDR, STR, and ADD only allow offsets that are a multiple of 4. Make some changes to better make use of these instructions: * Use word loads for anyext byte and halfword loads from the stack. * Enforce 4-byte alignment on objects accessed in this way, to ensure that the offset is valid. * Do the same for objects whose frame index is used, in order to avoid having to use more than one ADD to generate the frame index. * Correct how many bits of offset we think AddrModeT1_s has. Patch by John Brawn. llvm-svn: 230496
* Migrate ARM except for TTI, AsmPrinter, and frame loweringEric Christopher2015-01-291-11/+8
| | | | | | away from getSubtargetImpl. llvm-svn: 227399
* Move DataLayout back to the TargetMachine from TargetSubtargetInfoEric Christopher2015-01-261-1/+1
| | | | | | | | | | | | | | | | | | | derived classes. Since global data alignment, layout, and mangling is often based on the DataLayout, move it to the TargetMachine. This ensures that global data is going to be layed out and mangled consistently if the subtarget changes on a per function basis. Prior to this all targets(*) have had subtarget dependent code moved out and onto the TargetMachine. *One target hasn't been migrated as part of this change: R600. The R600 port has, as a subtarget feature, the size of pointers and this affects global data layout. I've currently hacked in a FIXME to enable progress, but the port needs to be updated to either pass the 64-bitness to the TargetMachine, or fix the DataLayout to avoid subtarget dependent features. llvm-svn: 227113
* Fix load-store optimizer on thumbv4tJonathan Roelofs2015-01-211-3/+14
| | | | | | | | | | Thumbv4t does not have lo->lo copies other than MOVS, and that can't be predicated. So emit MOVS when needed and bail if there's a predicate. http://reviews.llvm.org/D6592 llvm-svn: 226711
* Grab the subtarget info off of the MachineFunction rather thanEric Christopher2014-10-141-1/+1
| | | | | | indirecting through the TargetMachine. llvm-svn: 219674
* [Thumb] Make load/store optimizer less conservative.Moritz Roth2014-09-241-60/+195
| | | | | | | | | | | If it's safe to clobber the condition flags, we can do a few extra things: it's then possible to reset the base register writeback using a SUBS, so we can try to merge even if the base register isn't dead after the merged instruction. This is effectively a (heavily bug-fixed) rewrite of r208992. llvm-svn: 218386
* ARM load/store optimizer: Don't materialize a new base register withMoritz Roth2014-09-161-4/+15
| | | | | | | | | | | | | | | | | ADDS/SUBS unless it's safe to clobber the condition flags. If the merged instructions are in a range where the CPSR is live, e.g. between a CMP -> Bcc, we can't safely materialize a new base register. This problem is quite rare, I couldn't come up with a test case and I've never actually seen this happen in the tests I'm running - there is a potential trigger for this in LNT/oggenc (spills being inserted between a CMP/Bcc), but at the moment this isn't being merged. I'll try to reduce that into a small test case once I've committed my upcoming patch to make merging less conservative. llvm-svn: 217881
* Thumb1 load/store optimizer: Improve code to materialize new base register.Moritz Roth2014-08-211-5/+13
| | | | | | | | | | | | | There are two add-immediate instructions in Thumb1: tADDi8 and tADDi3. Only the latter supports using different source and destination registers, so whenever we materialize a new base register (at a certain offset) we'd do so by moving the base register value to the new register and then adding in place. This patch changes the code to use a single tADDi3 if the offset is small enough to fit in 3 bits. Differential Revision: http://reviews.llvm.org/D5006 llvm-svn: 216193
* Repace SmallPtrSet with SmallPtrSetImpl in function arguments to avoid ↵Craig Topper2014-08-211-1/+1
| | | | | | needing to mention the size. llvm-svn: 216158
* Revert "Repace SmallPtrSet with SmallPtrSetImpl in function arguments to ↵Craig Topper2014-08-181-1/+1
| | | | | | | | avoid needing to mention the size." Getting a weird buildbot failure that I need to investigate. llvm-svn: 215870
* Repace SmallPtrSet with SmallPtrSetImpl in function arguments to avoid ↵Craig Topper2014-08-171-1/+1
| | | | | | needing to mention the size. llvm-svn: 215868
* ARM: Fix and re-enable load/store optimizer for Thumb1.Moritz Roth2014-08-151-111/+8
| | | | | | | | | | | | | | | In a previous iteration of the pass, we would try to compensate for writeback by updating later instructions and/or inserting a SUBS to reset the base register if necessary. Since such a SUBS sets the condition flags it's not generally safe to do this. For now, only merge LDR/STRs if there is no writeback to the base register (LDM that loads into the base register) or the base register is killed by one of the merged instructions. These cases are clear wins both in terms of instruction count and performance. Also add three new test cases, and update the existing ones accordingly. llvm-svn: 215729
* ARM load/store optimizer: Compute BaseKill correctly.Moritz Roth2014-08-151-5/+11
| | | | | | | | | | | This adds some code back that was deleted in r92053. The location of the last merged memory operation needs to be kept up-to-date since MemOps may be in a different order to the original instruction stream to allow merging (since registers need to be in ascending order). Also simplify the logic to determine BaseKill using findRegisterUseOperandIdx to use an equivalent function call instead. llvm-svn: 215728
* Have MachineFunction cache a pointer to the subtarget to make lookupsEric Christopher2014-08-051-3/+3
| | | | | | | | | | | shorter/easier and have the DAG use that to do the same lookup. This can be used in the future for TargetMachine based caching lookups from the MachineFunction easily. Update the MIPS subtarget switching machinery to update this pointer at the same time it runs. llvm-svn: 214838
* Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher2014-08-041-6/+6
| | | | | | information and update all callers. No functional change. llvm-svn: 214781
* Fix memory leak of RegScavenger accidentally added in r211037.James Molloy2014-06-171-1/+3
| | | | llvm-svn: 211097
* Refactor the disabling of Thumb-1 LDM/STM generationJames Molloy2014-06-161-0/+4
| | | | | | | | Originally I switched the LD/ST optimizer off in TargetMachine as it was previously, but Eric has suggested he'd prefer that it be short-circuited in the pass itself. No functionality change. llvm-svn: 211037
* Fix a bug in the Thumb1 ARM Load/Store optimizerRenato Golin2014-06-101-7/+7
| | | | | | | | | | | | | | Previously, the basic block was searched for future uses of the base register, and if necessary any writeback to the base register was reset using a SUB instruction (e.g. before calling a function) just before such a use. However, this step happened *before* the merged LDM/STM instruction was built. So if there was (e.g.) a function call directly after the not-yet-formed LDM/STM, the pass would first insert a SUB instruction to reset the base register, and then (at the same location, incorrectly) insert the LDM/STM itself. This patch fixes PR19972. Patch by Moritz Roth. llvm-svn: 210542
* Fix the Load/Store optimization pass to work with Thumb1.James Molloy2014-05-161-34/+238
| | | | | | Patch by Moritz Roth! llvm-svn: 208992
* Enable the Load/Store optimization pass for Thumb1 but make it return ↵James Molloy2014-05-161-1/+10
| | | | | | | | immediately for now. Patch by Moritz Roth! llvm-svn: 208991
* Fix a few comment typos and style issues.James Molloy2014-05-161-16/+17
| | | | | | Patch by Moritz Roth! llvm-svn: 208990
* [C++] Use 'nullptr'. Target edition.Craig Topper2014-04-251-2/+2
| | | | llvm-svn: 207197
* [Modules] Fix potential ODR violations by sinking the DEBUG_TYPEChandler Carruth2014-04-221-1/+2
| | | | | | | definition below all of the header #include lines, lib/Target/... edition. llvm-svn: 206842
* Prune includes in ARM target.Craig Topper2014-03-221-1/+1
| | | | llvm-svn: 204548
* [C++11] Add 'override' keyword to virtual methods that override their base ↵Craig Topper2014-03-101-4/+4
| | | | | | class. llvm-svn: 203433
* [C++11] Replace llvm::next and llvm::prior with std::next and std::prev.Benjamin Kramer2014-03-021-13/+13
| | | | | | Remove the old functions. llvm-svn: 202636
* Now that we have C++11, turn simple functors into lambdas and remove a ton ↵Benjamin Kramer2014-03-011-12/+7
| | | | | | | | of boilerplate. No intended functionality change. llvm-svn: 202588
* ARM: correct liveness flags during ARMLoadStoreOptTim Northover2013-10-101-0/+77
| | | | | | | | | | | | | | | | | | | | | | When we had a sequence like: s1 = VLDRS [r0, 1], Q0<imp-def> s3 = VLDRS [r0, 2], Q0<imp-use,kill>, Q0<imp-def> s0 = VLDRS [r0, 0], Q0<imp-use,kill>, Q0<imp-def> s2 = VLDRS [r0, 4], Q0<imp-use,kill>, Q0<imp-def> we were gathering the {s0, s1} loads below the s3 load. This is fine, but confused the verifier since now the s3 load had Q0<imp-use> with no definition above it. This should mark such uses <undef> as well. The liveness structure at the beginning and end of the block is unaffected, and the true sN definitions should prevent any dodgy reorderings being introduced elsewhere. rdar://problem/15124449 llvm-svn: 192344
* Swift: Only build vldm/vstm with q register aligned register listsArnold Schwaighofer2013-09-041-1/+4
| | | | | | | | Unaligned vldm/vstm need more uops and therefore are slower in general on swift. radar://14522102 llvm-svn: 189961
* Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector ↵Craig Topper2013-07-141-7/+7
| | | | | | size. llvm-svn: 186274
* Simplify code.Craig Topper2013-07-101-6/+2
| | | | llvm-svn: 186013
* Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid ↵Craig Topper2013-07-041-4/+4
| | | | | | specifying the vector size. llvm-svn: 185606
* ARM: Remove a (false) dependency on the memoryoperand's value as we do not useQuentin Colombet2013-06-201-1/+2
| | | | | | | | | | it at the moment. This allows to form more paired loads even when stack coloring pass destroys the memoryoperand's value. <rdar://problem/13978317> llvm-svn: 184492
* Fix for PR14824, An ARM Load/Store Optimization bugHao Liu2013-04-181-1/+17
| | | | llvm-svn: 179751
* Reverting 178851 as it broke buildbotsRenato Golin2013-04-051-161/+10
| | | | llvm-svn: 178883
* Buildbot fix for r178851: mistake was in wrong ↵Stepan Dyatkovskiy2013-04-051-1/+1
| | | | | | TargetRegisterInfo::getRegClass usage. llvm-svn: 178854
* Fix for PR14824: "Optimization arm_ldst_opt inserts newly generated ↵Stepan Dyatkovskiy2013-04-051-10/+161
| | | | | | | | | | | | | | | | | instruction vldmia at incorrect position". Patch introduces memory operands tracking in ARMLoadStoreOpt::LoadStoreMultipleOpti. For each register it keeps the order of load operations as it was before optimization pass. It is kind of deep improvement of fix proposed by Hao: http://llvm.org/bugs/show_bug.cgi?id=14824#c4 But it also tracks conflicts between different register classes (e.g. D2 and S5). For more details see: Bug description: http://llvm.org/bugs/show_bug.cgi?id=14824 LLVM Commits discussion: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130311/167936.html http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130318/168688.html http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130325/169376.html http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130401/170238.html llvm-svn: 178851
* [arm load/store optimizer] When trying to merge a base update load/store, makeChad Rosier2013-03-251-1/+1
| | | | | | | | | | | sure the base register and would-be writeback register don't conflict for stores. This was already being done for loads. Unfortunately, it is rather difficult to create a test case for this issue. It was exposed in 450.soplex at LTO and requires unlucky register allocation. <rdar://13394908> llvm-svn: 177874
* Radar numbers don't belong in source code.Evan Cheng2013-02-211-1/+0
| | | | llvm-svn: 175775
* Move all of the header files which are involved in modelling the LLVM IRChandler Carruth2013-01-021-3/+3
| | | | | | | | | | | | | | | | | | | | | into their new header subdirectory: include/llvm/IR. This matches the directory structure of lib, and begins to correct a long standing point of file layout clutter in LLVM. There are still more header files to move here, but I wanted to handle them in separate commits to make tracking what files make sense at each layer easier. The only really questionable files here are the target intrinsic tablegen files. But that's a battle I'd rather not fight today. I've updated both CMake and Makefile build systems (I think, and my tests think, but I may have missed something). I've also re-sorted the includes throughout the project. I'll be committing updates to Clang, DragonEgg, and Polly momentarily. llvm-svn: 171366
* Add an MF argument to MI::copyImplicitOps().Jakob Stoklund Olesen2012-12-201-1/+1
| | | | | | | | | This function is often used to decorate dangling instructions, so a context reference is required to allocate memory for the operands. Also add a corresponding MachineInstrBuilder method. llvm-svn: 170797
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-11/+11
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
* Move TargetData to DataLayout.Micah Villmow2012-10-081-3/+3
| | | | llvm-svn: 165402
* Remove getARMRegisterNumbering and replace with calls intoEric Christopher2012-08-091-4/+2
| | | | | | | | | | | the register info for getEncodingValue. This builds on the small patch of yesterday to set HWEncoding in the register file. One (deprecated) use was turned into a hard number to avoid needing register info in the old JIT. llvm-svn: 161628
* Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass().Jakob Stoklund Olesen2012-05-071-1/+1
| | | | | | | | | | | | | The getPointerRegClass() hook can return register classes that depend on the calling convention of the current function (ptr_rc_tailcall). So far, we have been able to infer the calling convention from the subtarget alone, but as we add support for multiple calling conventions per target, that no longer works. Patch by Yiannis Tsiouris! llvm-svn: 156328
* ARM: Nuke remnant bogus code.Jim Grosbach2012-04-241-2/+0
| | | | | | | | r154362 was supposed to delete this bit, but obviously didn't. rdar://11305594 llvm-svn: 155465
* Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change ↵Craig Topper2012-04-201-1/+1
| | | | | | since they are equivalent. llvm-svn: 155188
* ARM LDR/LDRT has the same encoding collision as STR/STRT.Jim Grosbach2012-04-101-8/+7
| | | | | | Generalized logic of r154141. llvm-svn: 154362
* ARM: Don't form a t2LDRi8 or t2STRi8 with an offset of zero.Jim Grosbach2012-04-051-0/+8
| | | | | | | | | | | | | | | | | The load/store optimizer splits LDRD/STRD into two instructions when the register pairing doesn't work out. For negative offsets in Thumb2, it uses t2STRi8 to do that. That's fine, except for the case when the offset is in the range [-4,-1]. In that case, we'll also form a second t2STRi8 with the original offset plus 4, resulting in a t2STRi8 with a non-negative offset, which ends up as if it were an STRT, which is completely bogus. Similarly for loads. No testcase, unfortunately, as any I've been able to construct is both large and extremely fragile. rdar://11193937 llvm-svn: 154141
* Don't kill the base register when expanding strd.Jakob Stoklund Olesen2012-03-281-0/+4
| | | | | | | | | | | | | | When an strd instruction doesn't get the registers it wants, it can be expanded into two str instructions. Make sure the first str doesn't kill the base register in the case where the base and data registers are identical: t2STRi12 %R0<kill>, %R0, 4, pred:14, pred:%noreg t2STRi12 %R2<kill>, %R0, 8, pred:14, pred:%noreg <rdar://problem/11101911> llvm-svn: 153611
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