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path: root/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
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* Improve MachineMemOperand handling.Dan Gohman2009-09-251-3/+3
| | | | | | | | | | | | | | | | | | | | | - Allocate MachineMemOperands and MachineMemOperand lists in MachineFunctions. This eliminates MachineInstr's std::list member and allows the data to be created by isel and live for the remainder of codegen, avoiding a lot of copying and unnecessary translation. This also shrinks MemSDNode. - Delete MemOperandSDNode. Introduce MachineSDNode which has dedicated fields for MachineMemOperands. - Change MemSDNode to have a MachineMemOperand member instead of its own fields with the same information. This introduces some redundancy, but it's more consistent with what MachineInstr will eventually want. - Ignore alignment when searching for redundant loads for CSE, but remember the greatest alignment. Target-specific code which previously used MemOperandSDNodes with generic SDNodes now use MemIntrinsicSDNodes, with opcodes in a designated range so that the SelectionDAG framework knows that MachineMemOperand information is available. llvm-svn: 82794
* Update register class references to use the global constant ↵Jim Grosbach2009-09-111-1/+1
| | | | | | ARM::*RegisterClass names. llvm-svn: 81556
* Simplify RegScavenger::FindUnusedReg.Jakob Stoklund Olesen2009-08-181-6/+2
| | | | | | | | | - Drop the Candidates argument and fix all callers. Now that RegScavenger tracks available registers accurately, there is no need to restict the search. - Make sure that no aliases of the found register are in use. This was a potential bug. llvm-svn: 79369
* Push LLVMContexts through the IntegerType APIs.Owen Anderson2009-08-131-1/+4
| | | | llvm-svn: 78948
* Whitespace cleanup. Remove trailing whitespace.Jim Grosbach2009-08-111-2/+2
| | | | llvm-svn: 78666
* Code refactoring. No functionality change.Evan Cheng2009-08-081-22/+9
| | | | llvm-svn: 78455
* It turns out most of the thumb2 instructions are not allowed to touch SP. ↵Evan Cheng2009-08-071-4/+16
| | | | | | | | | | The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing. This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time. This fixes PR4659 and PR4682. llvm-svn: 78361
* Enable load / store multiple pass for Thumb2. It's not using ldrd / strd yet.Evan Cheng2009-08-041-6/+9
| | | | llvm-svn: 78104
* Thumb2 does not have ib (increment before) and da (decrement after) forms of ↵Evan Cheng2009-08-041-4/+10
| | | | | | ldm / stm. llvm-svn: 78057
* Load / store multiple pass fixes for Thumb2. Not enabled yet.Evan Cheng2009-08-041-76/+85
| | | | llvm-svn: 78031
* llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.Torok Edwin2009-07-141-3/+3
| | | | | | | | | This adds location info for all llvm_unreachable calls (which is a macro now) in !NDEBUG builds. In NDEBUG builds location info and the message is off (it only prints "UREACHABLE executed"). llvm-svn: 75640
* Major changes to Thumb (not Thumb2). Many 16-bit instructions either ↵Evan Cheng2009-07-111-1/+1
| | | | | | | | modifies CPSR when they are outside the IT blocks, or they can predicated when in Thumb2. Move the implicit def of CPSR to an optional def which defaults CPSR. This allows the 's' bit to be toggled dynamically. A side-effect of this change is asm printer is now using unified assembly. There are some minor clean ups and fixes as well. llvm-svn: 75359
* Remove a bogus assertion.Evan Cheng2009-07-101-2/+0
| | | | llvm-svn: 75206
* Initial support for load / store multiple opt pass Thumb2 support ↵Evan Cheng2009-07-091-55/+158
| | | | | | (post-allocation only). It's kind of there, but not quite. I'll return to this later. llvm-svn: 75190
* Change how so_imm and t2_so_imm are handled. At instruction selection time, ↵Evan Cheng2009-07-081-3/+2
| | | | | | the immediates are no longer encoded in the imm8 + rot format, that are left as it is. The encoding is now done in ams printing and code emission time instead. llvm-svn: 75048
* Implement changes from Chris's feedback.Torok Edwin2009-07-081-3/+3
| | | | | | Finish converting lib/Target. llvm-svn: 75043
* Start converting to new error handling API.Torok Edwin2009-07-081-3/+4
| | | | | | | cerr+abort -> llvm_report_error assert(0)+abort -> LLVM_UNREACHABLE (assert(0)+llvm_unreachable-> abort() included) llvm-svn: 75018
* Enable arm pre-allocation load / store multiple optimization pass.Evan Cheng2009-06-191-16/+36
| | | | llvm-svn: 73791
* Transfer dead markers when a ldrd is changed into a ldm or a pair of ldr.Evan Cheng2009-06-191-15/+20
| | | | llvm-svn: 73749
* - Update register allocation hint after coalescing. This is done by the ↵Evan Cheng2009-06-181-18/+48
| | | | | | | | | target since the hint is target dependent. This is important for ARM register pair hints. - Register allocator should resolve the second part of the hint (register number) before passing it to the target since it knows virtual register to physical register mapping. - More fixes to get ARM load / store double word working. llvm-svn: 73671
* Typo.Evan Cheng2009-06-151-1/+1
| | | | llvm-svn: 73422
* Do not form ldrd / strd if the two dests / srcs are the same. Code clean up.Evan Cheng2009-06-151-59/+73
| | | | llvm-svn: 73413
* Silence a warning.Evan Cheng2009-06-151-1/+1
| | | | llvm-svn: 73406
* Part 1.Evan Cheng2009-06-151-6/+197
| | | | | | | | | | | | | | | | | | | | | - Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent. - Allow targets to specify alternative register allocation orders based on allocation hint. Part 2. - Use the register allocation hint system to implement more aggressive load / store multiple formation. - Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g. v1025 = LDR v1024, 0 v1026 = LDR v1024, 0 => v1025,v1026 = LDRD v1024, 0 If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair. - Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions. This is work in progress, not yet enabled. llvm-svn: 73381
* Add a ARM specific pre-allocation pass that re-schedule loads / stores fromEvan Cheng2009-06-131-22/+314
| | | | | | | | | | | consecutive addresses togther. This makes it easier for the post-allocation pass to form ldm / stm. This is step 1. We are still missing a lot of ldm / stm opportunities because of register allocation are not done in the desired order. More enhancements coming. llvm-svn: 73291
* Changing allocation ordering from r3 ... r0 back to r0 ... r3. The order ↵Evan Cheng2009-06-051-5/+5
| | | | | | change no longer make sense after the coalescing changes we have made since then. llvm-svn: 72955
* When merging multiple load / store instructions. Use the DebugLoc of the ↵Evan Cheng2009-06-051-11/+16
| | | | | | first one. llvm-svn: 72952
* Code clean up: return vector by reference rather than by value. No ↵Evan Cheng2009-06-051-21/+21
| | | | | | functionality changes. llvm-svn: 72950
* Re-apply 72756 with fixes. One of those was introduced by we changed ↵Evan Cheng2009-06-041-1/+8
| | | | | | MachineInstrBuilder::addReg() interface. llvm-svn: 72826
* Temporarily revert 72756 for now.Evan Cheng2009-06-031-7/+0
| | | | llvm-svn: 72757
* Fold preceding / trailing base inc / dec into the single load / store as well.Evan Cheng2009-06-031-2/+9
| | | | llvm-svn: 72756
* Change MachineInstrBuilder::addReg() to take a flag instead of a list ofBill Wendling2009-05-131-9/+10
| | | | | | | | | | | | booleans. This gives a better indication of what the "addReg()" is doing. Remembering what all of those booleans mean isn't easy, especially if you aren't spending all of your time in that code. I took Jakob's suggestion and made it illegal to pass in "true" for the flag. This should hopefully prevent any unintended misuse of this (by reverting to the old way of using addReg()). llvm-svn: 71722
* Remove refs to non-DebugLoc versions of BuildMI from ARM.Dale Johannesen2009-02-131-7/+13
| | | | llvm-svn: 64429
* Switch the MachineOperand accessors back to the short names likeDan Gohman2008-10-031-3/+3
| | | | | | isReg, etc., from isRegister, etc. llvm-svn: 57006
* Tidy up several unbeseeming casts from pointer to intptr_t.Dan Gohman2008-09-041-1/+1
| | | | llvm-svn: 55779
* Rename MRegisterInfo to TargetRegisterInfo.Dan Gohman2008-02-101-3/+3
| | | | llvm-svn: 46930
* rename MachineInstr::setInstrDescriptor -> setDescChris Lattner2008-01-111-1/+1
| | | | llvm-svn: 45871
* rename TargetInstrDescriptor -> TargetInstrDesc.Chris Lattner2008-01-071-2/+2
| | | | | | | Make MachineInstr::getDesc return a reference instead of a pointer, since it can never be null. llvm-svn: 45695
* Move a bunch more accessors from TargetInstrInfo to TargetInstrDescriptorChris Lattner2008-01-071-1/+1
| | | | llvm-svn: 45680
* Rename MachineInstr::getInstrDescriptor -> getDesc(), which reflectsChris Lattner2008-01-071-1/+1
| | | | | | | | | | | | | | | that it is cheap and efficient to get. Move a variety of predicates from TargetInstrInfo into TargetInstrDescriptor, which makes it much easier to query a predicate when you don't have TII around. Now you can use MI->getDesc()->isBranch() instead of going through TII, and this is much more efficient anyway. Not all of the predicates have been moved over yet. Update old code that used MI->getInstrDescriptor()->Flags to use the new predicates in many places. llvm-svn: 45674
* Use MachineOperand::getImm instead of MachineOperand::getImmedValue. ↵Chris Lattner2007-12-301-1/+1
| | | | | | Likewise setImmedValue -> setImm llvm-svn: 45453
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+2
| | | | llvm-svn: 45418
* Avoid referencing deleted instruction.Evan Cheng2007-09-191-5/+26
| | | | llvm-svn: 42153
* Remove clobbersPred. Add an OptionalDefOperand to instructions which have ↵Evan Cheng2007-07-101-1/+1
| | | | | | the 's' bit. llvm-svn: 38501
* Reflects the chanegs made to PredicateOperand.Evan Cheng2007-07-051-41/+65
| | | | llvm-svn: 37898
* Add missing const qualifiers.Evan Cheng2007-05-291-2/+3
| | | | llvm-svn: 37342
* Add PredicateOperand to all ARM instructions that have the condition field.Evan Cheng2007-05-151-36/+60
| | | | llvm-svn: 37066
* Drop 'const'Devang Patel2007-05-031-2/+2
| | | | llvm-svn: 36662
* Use 'static const char' instead of 'static const int'.Devang Patel2007-05-021-2/+2
| | | | | | | Due to darwin gcc bug, one version of darwin linker coalesces static const int, which defauts PassID based pass identification. llvm-svn: 36652
* Do not use typeinfo to identify pass in pass manager.Devang Patel2007-05-011-0/+4
| | | | llvm-svn: 36632
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