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authorEvan Cheng <evan.cheng@apple.com>2009-08-04 21:12:13 +0000
committerEvan Cheng <evan.cheng@apple.com>2009-08-04 21:12:13 +0000
commit783b65b54658d2791f65a816372b54cad8c20247 (patch)
tree7d105a488703a5de5f0c4e933fc7bf95d69fa9de /llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
parentcd450bbbe52ecede3ce3596230a777f0cc9865d7 (diff)
downloadbcm5719-llvm-783b65b54658d2791f65a816372b54cad8c20247.tar.gz
bcm5719-llvm-783b65b54658d2791f65a816372b54cad8c20247.zip
Enable load / store multiple pass for Thumb2. It's not using ldrd / strd yet.
llvm-svn: 78104
Diffstat (limited to 'llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp')
-rw-r--r--llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp15
1 files changed, 9 insertions, 6 deletions
diff --git a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
index c6afbe93360..a81b790f9dc 100644
--- a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
+++ b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
@@ -615,12 +615,15 @@ bool ARMLoadStoreOpt::MergeBaseUpdateLoadStore(MachineBasicBlock &MBB,
return false;
bool isDPR = NewOpc == ARM::FLDMD || NewOpc == ARM::FSTMD;
- unsigned Offset = isAM5
- ? ARM_AM::getAM5Opc((AddSub == ARM_AM::sub) ? ARM_AM::db : ARM_AM::ia,
- true, isDPR ? 2 : 1)
- : (isAM2
- ? ARM_AM::getAM2Opc(AddSub, Bytes, ARM_AM::no_shift)
- : Bytes);
+ unsigned Offset = 0;
+ if (isAM5)
+ Offset = ARM_AM::getAM5Opc((AddSub == ARM_AM::sub)
+ ? ARM_AM::db
+ : ARM_AM::ia, true, (isDPR ? 2 : 1));
+ else if (isAM2)
+ Offset = ARM_AM::getAM2Opc(AddSub, Bytes, ARM_AM::no_shift);
+ else
+ Offset = AddSub == ARM_AM::sub ? -Bytes : Bytes;
if (isLd) {
if (isAM5)
// FLDMS, FLDMD
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