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* ARM: Use the PICADD opcode calculated.Jim Grosbach2013-09-101-2/+6
| | | | | | | | | | | | | | We were figuring out whether to use tPICADD or PICADD, then just using tPICADD unconditionally anyway. Oops. A testcase from someone familiar enough with ELF to produce one would be appreciated. The existing PIC testcase correctly verifies the .s generated, but that doesn't catch this bug, which only showed up in direct-to-object mode. http://llvm.org/bugs/show_bug.cgi?id=17180 llvm-svn: 190417
* ARM: Fix ELF global base reg intialization.Jim Grosbach2013-08-261-3/+8
| | | | | | | | | | | | | | | | | | The create machine code wasn't properly in SSA, which the machine verifier properly complains about. Now that fast-isel is closer to verifier clean, errors like this show up more clearly. Additionally, the Thumb pseudo tPICADD was used for both ARM and Thumb mode functions, which is obviously wrong. Fix that along the way. Test case is part of the following commit which will finish making an additional fast-isel test verifier clean an enable it for the regression test suite. This commit is separate since its not just a verifier cleanup, but an actual correctness issue. rdar://12594152 (for the fast-isel verifier aspects) llvm-svn: 189269
* When initializing the PIC global base register on ARM/ELF add pc to fix the ↵Benjamin Kramer2013-08-161-0/+4
| | | | | | | | | | address. This unbreaks PIC with fast isel on ELF targets (PR16717). The output matches what GCC and SDag do for PIC but may not cover all of the many flavors of PIC that exist. llvm-svn: 188551
* Create a constant pool symbol for the GOT in the ARMCGBR the same way weChandler Carruth2013-07-271-7/+8
| | | | | | | | | | | | | | do in the SDag when lowering references to the GOT: use ARMConstantPoolSymbol rather than creating a dummy global variable. The computation of the alignment still feels weird (it uses IR types and datalayout) but it preserves the exact previous behavior. This change fixes the memory leak of the global variable detected on the valgrind leak checking bot. Thanks to Benjamin Kramer for pointing me at ARMConstantPoolSymbol to handle this use case. llvm-svn: 187303
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-071-1/+1
| | | | | | the internals of TargetMachine could change. llvm-svn: 183488
* Move all of the header files which are involved in modelling the LLVM IRChandler Carruth2013-01-021-2/+2
| | | | | | | | | | | | | | | | | | | | | into their new header subdirectory: include/llvm/IR. This matches the directory structure of lib, and begins to correct a long standing point of file layout clutter in LLVM. There are still more header files to move here, but I wanted to handle them in separate commits to make tracking what files make sense at each layer easier. The only really questionable files here are the target intrinsic tablegen files. But that's a battle I'd rather not fight today. I've updated both CMake and Makefile build systems (I think, and my tests think, but I may have missed something). I've also re-sorted the includes throughout the project. I'll be committing updates to Clang, DragonEgg, and Polly momentarily. llvm-svn: 171366
* Move TargetData to DataLayout.Micah Villmow2012-10-081-1/+1
| | | | llvm-svn: 165402
* [arm-fast-isel] Add support for ELF PIC.Jush Lu2012-09-271-0/+62
| | | | | | | This is a preliminary step towards ELF support; currently ARMFastISel hasn't been used for ELF object files yet. llvm-svn: 164759
* ARM: Define generic HINT instruction.Jim Grosbach2012-06-181-1/+2
| | | | | | | | | | | The NOP, WFE, WFI, SEV and YIELD instructions are all hints w/ a different immediate value in bits [7,0]. Define a generic HINT instruction and refactor NOP, WFI, WFI, SEV and YIELD to be assembly aliases of that. rdar://11600518 llvm-svn: 158674
* ARM implement TargetInstrInfo::getNoopForMachoTarget()Jim Grosbach2012-02-281-0/+17
| | | | | | | | | | | | | | Without this hook, functions w/ a completely empty body (including no epilogue) will cause an MCEmitter assertion failure. For example, define internal fastcc void @empty_function() { unreachable } rdar://10947471 llvm-svn: 151673
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu2012-02-181-1/+1
| | | | | | MSP430, PPC, PTX, Sparc, X86, XCore. llvm-svn: 150878
* invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We ↵Owen Anderson2011-08-261-2/+4
| | | | | | were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure. llvm-svn: 138653
* Split am2offset into register addend and immediate addend forms, necessary ↵Owen Anderson2011-07-261-6/+12
| | | | | | for allowing the fixed-length disassembler to distinguish between SBFX and STR_PRE. llvm-svn: 136141
* Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ↵Evan Cheng2011-07-201-1/+1
| | | | | | ARM MC code from target. llvm-svn: 135636
* Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.incEvan Cheng2011-06-281-1/+0
| | | | llvm-svn: 134024
* Eliminate ARM::MOVi2pieces. Just use MOVi32imm and expand it to either ↵Evan Cheng2010-11-121-24/+0
| | | | | | movi+orr or movw+movt depending on the subtarget. llvm-svn: 118938
* Convert ARM::MOVi2pieces to a true pseudo-instruction and expand it inJim Grosbach2010-10-291-2/+1
| | | | | | the ARMExpandPseudos pass rather than during the asm lowering. llvm-svn: 117714
* Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, likeJim Grosbach2010-10-271-2/+2
| | | | | | | | the LDR instructions have. This makes the literal/register forms of the instructions explicit and allows us to assign scheduling itineraries appropriately. rdar://8477752 llvm-svn: 117505
* Split ARM::LDRB into LDRBi12 and LDRBrs. Adjust accordingly. Continuing onJim Grosbach2010-10-271-1/+1
| | | | | | rdar://8477752. llvm-svn: 117419
* First part of refactoring ARM addrmode2 (load/store) instructions to be moreJim Grosbach2010-10-261-1/+1
| | | | | | | | explicit about the operands. Split out the different variants into separate instructions. This gives us the ability to, among other things, assign different scheduling itineraries to the variants. rdar://8477752. llvm-svn: 117409
* Slightly change the meaning of the reMaterialize target hook when the originalJakob Stoklund Olesen2010-06-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | instruction defines subregisters. Any existing subreg indices on the original instruction are preserved or composed with the new subreg index. Also substitute multiple operands mentioning the original register by using the new MachineInstr::substituteRegister() function. This is necessary because there will soon be <imp-def> operands added to non read-modify-write partial definitions. This instruction: %reg1234:foo = FLAP %reg1234<imp-def> will reMaterialize(%reg3333, bar) like this: %reg3333:bar-foo = FLAP %reg333:bar<imp-def> Finally, replace the TargetRegisterInfo pointer argument with a reference to indicate that it cannot be NULL. llvm-svn: 105358
* Remove the target hook TargetInstrInfo::BlockHasNoFallThrough in favor ofDan Gohman2009-12-051-19/+0
| | | | | | | MachineBasicBlock::canFallThrough(), which is target-independent and more thorough. llvm-svn: 90634
* - Change TargetInstrInfo::reMaterialize to pass in TargetRegisterInfo.Evan Cheng2009-11-141-3/+3
| | | | | | | | - If destination is a physical register and it has a subreg index, use the sub-register instead. This fixes PR5423. llvm-svn: 88745
* Refactor code.Evan Cheng2009-11-081-11/+8
| | | | llvm-svn: 86423
* - Add pseudo instructions tLDRpci_pic and t2LDRpci_pic which does a pc-relativeEvan Cheng2009-11-061-5/+12
| | | | | | | | | | | | load of a GV from constantpool and then add pc. It allows the code sequence to be rematerializable so it would be hoisted by machine licm. - Add a late pass to break these pseudo instructions into a number of real instructions. Also move the code in Thumb2 IT pass that breaks up t2MOVi32imm to this pass. This is done before post regalloc scheduling to allow the scheduler to proper schedule these instructions. It also allow them to be if-converted and shrunk by later passes. llvm-svn: 86304
* Use NEON reg-reg moves, where profitable. This reduces "domain-cross" ↵Anton Korobeynikov2009-11-021-1/+1
| | | | | | stalls, when we used to mix vfp and neon code (the former were used for reg-reg moves) llvm-svn: 85764
* Add a Thumb BRIND pattern. Change the ARM BRIND assembly to separate theBob Wilson2009-10-281-0/+1
| | | | | | | opcode and operand with a tab. Check for these instructions in the usual places. llvm-svn: 85411
* Trim more includes.Evan Cheng2009-10-221-1/+0
| | | | llvm-svn: 84832
* Make ARM and Thumb2 32-bit immediate materialization into a single 32-bit pseudoEvan Cheng2009-09-281-1/+0
| | | | | | | | | instruction. This makes it re-materializable. Thumb2 will split it back out into two instructions so IT pass will generate the right mask. Also, this expose opportunies to optimize the movw to a 16-bit move. llvm-svn: 82982
* Fix thinko in my recent movt commit: it's not safe to remat movt, since it ↵Anton Korobeynikov2009-09-281-2/+0
| | | | | | | | has input reg argument. Disable rematting of it for now. llvm-svn: 82975
* Use movt/movw pair to materialize 32 bit constants on ARMv6T2+.Anton Korobeynikov2009-09-271-0/+3
| | | | | | This should be better than single load from constpool. llvm-svn: 82948
* Rename TargetAsmInfo (and its subclasses) to MCAsmInfo.Chris Lattner2009-08-221-1/+1
| | | | llvm-svn: 79763
* Remove ARM specific getInlineAsmLength. We'll rely on the simpler (and ↵Evan Cheng2009-08-041-160/+0
| | | | | | faster) generic algorithm for now. If more accurate computation is needed, we'll rely on the disassembler. llvm-svn: 78032
* Move the getInlineAsmLength virtual method from TAI to TII, whereChris Lattner2009-08-021-5/+164
| | | | | | | | | | the only real caller (GetFunctionSizeInBytes) uses it. The custom ARM implementation of this is basically reimplementing an assembler poorly for negligible gain. It should be removed IMNSHO, but I'll leave that to ARMish folks to decide. llvm-svn: 77877
* - More refactoring. This gets rid of all of the getOpcode calls.Evan Cheng2009-07-281-13/+0
| | | | | | | | | | | - This change also makes it possible to switch between ARM / Thumb on a per-function basis. - Fixed thumb2 routine which expand reg + arbitrary immediate. It was using using ARM so_imm logic. - Use movw and movt to do reg + imm when profitable. - Other code clean ups and minor optimizations. llvm-svn: 77300
* More DCE.Evan Cheng2009-07-271-4/+0
| | | | llvm-svn: 77231
* Get rid of more dead code.Evan Cheng2009-07-271-2/+0
| | | | llvm-svn: 77227
* Get rid of some more getOpcode calls.Evan Cheng2009-07-271-3/+0
| | | | | | This also fixes potential problems in ARMBaseInstrInfo routines not recognizing thumb1 instructions when 32-bit and 16-bit instructions mix. llvm-svn: 77218
* Use t2LDRi12 and t2STRi12 to load / store to / from stack frames. Eliminate ↵Evan Cheng2009-07-271-2/+0
| | | | | | more getOpcode calls. llvm-svn: 77181
* Change Thumb2 jumptable codegen to one that uses two level jumps:Evan Cheng2009-07-251-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before: adr r12, #LJTI3_0_0 ldr pc, [r12, +r0, lsl #2] LJTI3_0_0: .long LBB3_24 .long LBB3_30 .long LBB3_31 .long LBB3_32 After: adr r12, #LJTI3_0_0 add pc, r12, +r0, lsl #2 LJTI3_0_0: b.w LBB3_24 b.w LBB3_30 b.w LBB3_31 b.w LBB3_32 This has several advantages. 1. This will make it easier to optimize this to a TBB / TBH instruction + (smaller) table. 2. This eliminate the need for ugly asm printer hack to force the address into thumb addresses (bit 0 is one). 3. Same codegen for pic and non-pic. 4. This eliminate the need to align the table so constantpool island pass won't have to over-estimate the size. Based on my calculation, the later is probably slightly faster as well since ldr pc with shifter address is very slow. That is, it should be a win as long as the HW implementation can do a reasonable job of branch predict the second branch. llvm-svn: 77024
* FLDD, FLDS, FCPYD, FCPYS, FSTD, FSTS, VMOVD, VMOVQ maps to the same ↵Evan Cheng2009-07-241-8/+0
| | | | | | instructions on all sub-targets. llvm-svn: 76925
* Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index ↵David Goodwin2009-07-241-7/+4
| | | | | | elimination more exactly for Thumb-2 to get better code gen. llvm-svn: 76919
* Fix frame index elimination to correctly handle thumb-2 addressing modes ↵David Goodwin2009-07-231-0/+5
| | | | | | that don't allow negative offsets. During frame elimination convert *i12 opcode to a *i8 when necessary due to a negative offset. llvm-svn: 76883
* Let callers decide the sub-register index on the def operand of ↵Evan Cheng2009-07-161-2/+2
| | | | | | | | rematerialized instructions. Avoid remat'ing instructions whose def have sub-register indices for now. It's just really really hard to get all the cases right. llvm-svn: 75900
* Generalize opcode selection in ARMBaseRegisterInfo.David Goodwin2009-07-081-1/+2
| | | | llvm-svn: 75036
* Checkpoint Thumb2 Instr info work. Generalized base code so that it can be ↵David Goodwin2009-07-081-827/+48
| | | | | | shared between ARM and Thumb2. Not yet activated because register information must be generalized first. llvm-svn: 75010
* Checkpoint refactoring of ThumbInstrInfo and ThumbRegisterInfo into ↵David Goodwin2009-07-021-293/+306
| | | | | | Thumb1InstrInfo, Thumb2InstrInfo, Thumb1RegisterInfo and Thumb2RegisterInfo. Move methods from ARMInstrInfo to ARMBaseInstrInfo to prepare for sharing with Thumb2. llvm-svn: 74731
* Handle IMPLICIT_DEF with isUndef operand marker, part 2. This patch moves ↵Evan Cheng2009-07-011-8/+26
| | | | | | the code to annotate machineoperands to LiveIntervalAnalysis. It also add markers for implicit_def that define physical registers. The rest, is just a lot of details. llvm-svn: 74580
* Improve Thumb-2 jump table support.David Goodwin2009-06-301-5/+9
| | | | llvm-svn: 74549
* Add conditional and unconditional thumb-2 branch. Add thumb-2 jump table.David Goodwin2009-06-301-17/+30
| | | | llvm-svn: 74543
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