Change Thumb2 jumptable codegen to one that uses two level jumps:

Before:
      adr r12, #LJTI3_0_0
      ldr pc, [r12, +r0, lsl #2]
LJTI3_0_0:
      .long    LBB3_24
      .long    LBB3_30
      .long    LBB3_31
      .long    LBB3_32

After:
      adr r12, #LJTI3_0_0
      add pc, r12, +r0, lsl #2
LJTI3_0_0:
      b.w    LBB3_24
      b.w    LBB3_30
      b.w    LBB3_31
      b.w    LBB3_32

This has several advantages.
1. This will make it easier to optimize this to a TBB / TBH instruction +
   (smaller) table.
2. This eliminate the need for ugly asm printer hack to force the address
   into thumb addresses (bit 0 is one).
3. Same codegen for pic and non-pic.
4. This eliminate the need to align the table so constantpool island pass
   won't have to over-estimate the size.

Based on my calculation, the later is probably slightly faster as well since
ldr pc with shifter address is very slow. That is, it should be a win as long
as the HW implementation can do a reasonable job of branch predict the second
branch.

llvm-svn: 77024

1 files changed, 0 insertions, 3 deletions

diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.cpp b/llvm/lib/Target/ARM/ARMInstrInfo.cpp
index 56a6b0b1d8c..0f649d4e933 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.cpp
@@ -70,9 +70,6 @@ getOpcode(ARMII::Op Op) const {
   case ARMII::ADDrr: return ARM::ADDrr;
   case ARMII::B: return ARM::B;
   case ARMII::Bcc: return ARM::Bcc;
-  case ARMII::BR_JTr: return ARM::BR_JTr;
-  case ARMII::BR_JTm: return ARM::BR_JTm;
-  case ARMII::BR_JTadd: return ARM::BR_JTadd;
   case ARMII::BX_RET: return ARM::BX_RET;
   case ARMII::LDRrr: return ARM::LDR;
   case ARMII::LDRri: return 0;