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path: root/llvm/lib/Target/ARM/ARMInstrInfo.cpp
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* Rename TargetAsmInfo (and its subclasses) to MCAsmInfo.Chris Lattner2009-08-221-1/+1
| | | | llvm-svn: 79763
* Remove ARM specific getInlineAsmLength. We'll rely on the simpler (and ↵Evan Cheng2009-08-041-160/+0
| | | | | | faster) generic algorithm for now. If more accurate computation is needed, we'll rely on the disassembler. llvm-svn: 78032
* Move the getInlineAsmLength virtual method from TAI to TII, whereChris Lattner2009-08-021-5/+164
| | | | | | | | | | the only real caller (GetFunctionSizeInBytes) uses it. The custom ARM implementation of this is basically reimplementing an assembler poorly for negligible gain. It should be removed IMNSHO, but I'll leave that to ARMish folks to decide. llvm-svn: 77877
* - More refactoring. This gets rid of all of the getOpcode calls.Evan Cheng2009-07-281-13/+0
| | | | | | | | | | | - This change also makes it possible to switch between ARM / Thumb on a per-function basis. - Fixed thumb2 routine which expand reg + arbitrary immediate. It was using using ARM so_imm logic. - Use movw and movt to do reg + imm when profitable. - Other code clean ups and minor optimizations. llvm-svn: 77300
* More DCE.Evan Cheng2009-07-271-4/+0
| | | | llvm-svn: 77231
* Get rid of more dead code.Evan Cheng2009-07-271-2/+0
| | | | llvm-svn: 77227
* Get rid of some more getOpcode calls.Evan Cheng2009-07-271-3/+0
| | | | | | This also fixes potential problems in ARMBaseInstrInfo routines not recognizing thumb1 instructions when 32-bit and 16-bit instructions mix. llvm-svn: 77218
* Use t2LDRi12 and t2STRi12 to load / store to / from stack frames. Eliminate ↵Evan Cheng2009-07-271-2/+0
| | | | | | more getOpcode calls. llvm-svn: 77181
* Change Thumb2 jumptable codegen to one that uses two level jumps:Evan Cheng2009-07-251-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before: adr r12, #LJTI3_0_0 ldr pc, [r12, +r0, lsl #2] LJTI3_0_0: .long LBB3_24 .long LBB3_30 .long LBB3_31 .long LBB3_32 After: adr r12, #LJTI3_0_0 add pc, r12, +r0, lsl #2 LJTI3_0_0: b.w LBB3_24 b.w LBB3_30 b.w LBB3_31 b.w LBB3_32 This has several advantages. 1. This will make it easier to optimize this to a TBB / TBH instruction + (smaller) table. 2. This eliminate the need for ugly asm printer hack to force the address into thumb addresses (bit 0 is one). 3. Same codegen for pic and non-pic. 4. This eliminate the need to align the table so constantpool island pass won't have to over-estimate the size. Based on my calculation, the later is probably slightly faster as well since ldr pc with shifter address is very slow. That is, it should be a win as long as the HW implementation can do a reasonable job of branch predict the second branch. llvm-svn: 77024
* FLDD, FLDS, FCPYD, FCPYS, FSTD, FSTS, VMOVD, VMOVQ maps to the same ↵Evan Cheng2009-07-241-8/+0
| | | | | | instructions on all sub-targets. llvm-svn: 76925
* Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index ↵David Goodwin2009-07-241-7/+4
| | | | | | elimination more exactly for Thumb-2 to get better code gen. llvm-svn: 76919
* Fix frame index elimination to correctly handle thumb-2 addressing modes ↵David Goodwin2009-07-231-0/+5
| | | | | | that don't allow negative offsets. During frame elimination convert *i12 opcode to a *i8 when necessary due to a negative offset. llvm-svn: 76883
* Let callers decide the sub-register index on the def operand of ↵Evan Cheng2009-07-161-2/+2
| | | | | | | | rematerialized instructions. Avoid remat'ing instructions whose def have sub-register indices for now. It's just really really hard to get all the cases right. llvm-svn: 75900
* Generalize opcode selection in ARMBaseRegisterInfo.David Goodwin2009-07-081-1/+2
| | | | llvm-svn: 75036
* Checkpoint Thumb2 Instr info work. Generalized base code so that it can be ↵David Goodwin2009-07-081-827/+48
| | | | | | shared between ARM and Thumb2. Not yet activated because register information must be generalized first. llvm-svn: 75010
* Checkpoint refactoring of ThumbInstrInfo and ThumbRegisterInfo into ↵David Goodwin2009-07-021-293/+306
| | | | | | Thumb1InstrInfo, Thumb2InstrInfo, Thumb1RegisterInfo and Thumb2RegisterInfo. Move methods from ARMInstrInfo to ARMBaseInstrInfo to prepare for sharing with Thumb2. llvm-svn: 74731
* Handle IMPLICIT_DEF with isUndef operand marker, part 2. This patch moves ↵Evan Cheng2009-07-011-8/+26
| | | | | | the code to annotate machineoperands to LiveIntervalAnalysis. It also add markers for implicit_def that define physical registers. The rest, is just a lot of details. llvm-svn: 74580
* Improve Thumb-2 jump table support.David Goodwin2009-06-301-5/+9
| | | | llvm-svn: 74549
* Add conditional and unconditional thumb-2 branch. Add thumb-2 jump table.David Goodwin2009-06-301-17/+30
| | | | llvm-svn: 74543
* Simplify a bitAnton Korobeynikov2009-06-271-3/+5
| | | | llvm-svn: 74385
* ARM refactoring. Step 2: split RegisterInfoAnton Korobeynikov2009-06-271-30/+11
| | | | llvm-svn: 74384
* Split thumb-related stuff into separate classes.Anton Korobeynikov2009-06-261-211/+56
| | | | | | Step 1: ARMInstructionInfo => {ARM,Thumb}InstructionInfo llvm-svn: 74329
* Add support for ARM's Advanced SIMD (NEON) instruction set.Bob Wilson2009-06-221-0/+8
| | | | | | | This is still a work in progress but most of the NEON instruction set is supported. llvm-svn: 73919
* GNU as refuses to assemble "pop {}" instruction. Do not emit suchAnton Korobeynikov2009-06-161-2/+6
| | | | | | | (this is the case when we have thumb vararg function with single callee-saved register, which is handled separately). llvm-svn: 73529
* Update the names of the exception handling sjlj instrinsics toJim Grosbach2009-05-141-1/+1
| | | | | | | | | llvm.eh.sjlj.* for better clarity as to their purpose and scope. Add a description of llvm.eh.sjlj.setjmp to ExceptionHandling.html. (llvm.eh.sjlj.longjmp documentation coming when that implementation is added). llvm-svn: 71758
* Change MachineInstrBuilder::addReg() to take a flag instead of a list ofBill Wendling2009-05-131-13/+13
| | | | | | | | | | | | booleans. This gives a better indication of what the "addReg()" is doing. Remembering what all of those booleans mean isn't easy, especially if you aren't spending all of your time in that code. I took Jakob's suggestion and made it illegal to pass in "true" for the flag. This should hopefully prevent any unintended misuse of this (by reverting to the old way of using addReg()). llvm-svn: 71722
* Add support for GCC compatible builtin setjmp and longjmp intrinsics. This isJim Grosbach2009-05-121-0/+1
| | | | | | | a supporting preliminary patch for GCC-compatible SjLJ exception handling. Note that these intrinsics are not designed to be invoked directly by the user, but rather used by the front-end as target hooks for exception handling. llvm-svn: 71610
* PR2985 / <rdar://problem/6584986>Jim Grosbach2009-04-071-27/+62
| | | | | | | | | | When compiling in Thumb mode, only the low (R0-R7) registers are available for most instructions. Breaking the low registers into a new register class handles this. Uses of R12, SP, etc, are handled explicitly where needed with copies inserted to move results into low registers where the rest of the code generator can deal with them. llvm-svn: 68545
* Wrap some lines to fix indentation problems.Bob Wilson2009-04-031-30/+36
| | | | llvm-svn: 68405
* Fix some comments.Bob Wilson2009-04-031-5/+5
| | | | llvm-svn: 68404
* Factor out the code to add a MachineOperand to a MachineInstrBuilder.Dan Gohman2009-02-181-18/+4
| | | | llvm-svn: 64891
* Remove refs to non-DebugLoc versions of BuildMI from ARM.Dale Johannesen2009-02-131-5/+8
| | | | llvm-svn: 64429
* Eliminate a couple of non-DebugLoc BuildMI variants.Dale Johannesen2009-02-121-4/+6
| | | | | | Modify callers. llvm-svn: 64409
* Move debug loc info along when the spiller creates new instructions.Bill Wendling2009-02-121-36/+65
| | | | llvm-svn: 64342
* Turns out AnalyzeBranch can modify the mbb being analyzed. This is a nastyEvan Cheng2009-02-091-3/+6
| | | | | | | | suprise to some callers, e.g. register coalescer. For now, add an parameter that tells AnalyzeBranch whether it's safe to modify the mbb. A better solution is out there, but I don't have time to deal with it right now. llvm-svn: 64124
* Move getPointerRegClass from TargetInstrInfo to TargetRegisterInfo.Evan Cheng2009-02-061-3/+0
| | | | llvm-svn: 63938
* Create DebugLoc information in FastISel. Several temporary methods wereBill Wendling2009-02-031-1/+1
| | | | | | | created. Specifically, those BuildMIs which use "DebugLoc::getUnknownLoc()". I'll remove them soon. llvm-svn: 63584
* Change TargetInstrInfo::isMoveInstr to return source and destination ↵Evan Cheng2009-01-201-1/+4
| | | | | | sub-register indices as well. llvm-svn: 62600
* Preliminary ARM debug support based on patch by Mikael of FlexyCore.Evan Cheng2008-12-101-3/+11
| | | | llvm-svn: 60851
* Split foldMemoryOperand into public non-virtual and protected virtualDan Gohman2008-12-031-3/+3
| | | | | | | parts, and add target-independent code to add/preserve MachineMemOperands. llvm-svn: 60488
* Add more const qualifiers. This fixes build breakage from r59540.Dan Gohman2008-11-181-2/+4
| | | | llvm-svn: 59542
* Minor code restructuring. No functionality change.Evan Cheng2008-11-031-6/+6
| | | | llvm-svn: 58643
* Const-ify several TargetInstrInfo methods.Dan Gohman2008-10-161-4/+4
| | | | llvm-svn: 57622
* Switch the MachineOperand accessors back to the short names likeDan Gohman2008-10-031-23/+23
| | | | | | isReg, etc., from isRegister, etc. llvm-svn: 57006
* Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy ↵Owen Anderson2008-08-261-4/+6
| | | | | | | | | requested was inserted or not. This allows bitcast in fast isel to properly handle the case where an appropriate reg-to-reg copy is not available. llvm-svn: 55375
* Convert uses of std::vector in TargetInstrInfo to SmallVector. This change ↵Owen Anderson2008-08-141-6/+6
| | | | | | had to be propoagated down into all the targets and up into all clients of this API. llvm-svn: 54802
* Pool-allocation for MachineInstrs, MachineBasicBlocks, andDan Gohman2008-07-071-24/+25
| | | | | | | | | | | MachineMemOperands. The pools are owned by MachineFunctions. This drastically reduces the number of calls to malloc/free made during the "Emit" phase of scheduling, as well as later phases in CodeGen. Combined with other changes, this speeds up the "instruction selection" phase of CodeGen by 10% in some cases. llvm-svn: 53212
* - Remove calls to copyKillDeadInfo which is an N^2 function. Instead, ↵Evan Cheng2008-07-031-14/+19
| | | | | | | | propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc. - Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list. llvm-svn: 53097
* Make LiveVariables even more optional, by making it optional in the call to ↵Owen Anderson2008-07-021-17/+20
| | | | | | | | TargetInstrInfo::convertToThreeAddressInstruction Also, if LV isn't around, then TwoAddr doesn't need to be updating flags, since they won't have been set in the first place. llvm-svn: 53058
* Split ISD::LABEL into ISD::DBG_LABEL and ISD::EH_LABEL, eliminatingDan Gohman2008-07-011-1/+1
| | | | | | | | | | | | | | | | the need for a flavor operand, and add a new SDNode subclass, LabelSDNode, for use with them to eliminate the need for a label id operand. Change instruction selection to let these label nodes through unmodified instead of creating copies of them. Teach the MachineInstr emitter how to emit a MachineInstr directly from an ISD label node. This avoids the need for allocating SDNodes for the label id and flavor value, as well as SDNodes for each of the post-isel label, label id, and label flavor. llvm-svn: 52943
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