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path: root/llvm/lib/Target/ARM/ARMISelLowering.h
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* Reland "[ARM] push LR before __gnu_mcount_nc"Jian Cai2019-08-161-0/+2
* Revert "[ARM] push LR before __gnu_mcount_nc"Jian Cai2019-08-161-2/+0
* [ARM] push LR before __gnu_mcount_ncJian Cai2019-08-161-0/+2
* [ARM] Don't pretend we know how to generate MVE VLDnDavid Green2019-08-161-1/+1
* [ARM] Lower "(x<<c) > 0x80000000U" to "lsls" on Thumb1.Eli Friedman2019-07-311-0/+1
* [ARM] Rewrite how VCMP are lowered, using a single nodeDavid Green2019-07-241-14/+2
* [ARM] Better OR's for MVE comparesDavid Green2019-07-241-0/+2
* [ARM] MVE predicate register supportDavid Green2019-07-241-0/+2
* [ARM] MVE integer compares and selectsDavid Green2019-07-241-0/+2
* [ARM][LowOverheadLoops] Fix branch target codegenSam Parker2019-07-231-0/+2
* [ARM] Rename NEONModImm to VMOVModImm. NFCDavid Green2019-07-231-1/+1
* [ARM] Adjust how NEON shifts are loweredDavid Green2019-07-151-17/+21
* [ARM] Add support for MSVC stack cookie checkingMartin Storsjo2019-07-071-0/+4
* [ARM] MVE VMOV immediate handlingDavid Green2019-07-051-0/+1
* [Codegen][X86][AArch64][ARM][PowerPC] Inc-of-add vs sub-of-not (PR42457)Roman Lebedev2019-07-031-0/+3
* [ARM] MVE: allow soft-float ABI to pass vector types.Simon Tatham2019-07-021-0/+1
* [ARM] Stop using scalar FP instructions in integer-only MVE mode.Simon Tatham2019-07-021-0/+2
* [ARM] WLS/LE Code GenerationSam Parker2019-07-011-0/+2
* [ARM] Add support for the MVE long shift instructionsSam Tebbs2019-06-281-0/+4
* [ARM] Widening loads and narrowing storesDavid Green2019-06-281-0/+1
* [ARM] MVE vector shufflesDavid Green2019-06-281-1/+2
* [ARM] Code-generation infrastructure for MVE.Simon Tatham2019-06-251-0/+1
* [TargetLowering] Add MachineMemOperand::Flags to allowsMemoryAccess tests (PR...Simon Pilgrim2019-06-121-0/+1
* [ARM][FIX] Ran out of registers due tail recursionDiogo N. Sampaio2019-06-031-9/+7
* [AMDGPU] Divergence driven ISel. Assign register class for cross block va...Alexander Timofeev2019-05-261-1/+2
* Revert r361644, "[AMDGPU] Divergence driven ISel. Assign register class for c...Peter Collingbourne2019-05-251-2/+1
* [AMDGPU] Divergence driven ISel. Assign register class for cross block values...Alexander Timofeev2019-05-241-1/+2
* [TargetLowering] Change getOptimalMemOpType to take a function attribute listSjoerd Meijer2019-04-301-1/+1
* [TargetLowering] Rename preferShiftsToClearExtremeBits and shouldFoldShiftPai...Simon Pilgrim2019-04-161-2/+2
* [SelectionDAG] Handle unary SelectPatternFlavor for ABS case in SelectionDAGB...Simon Pilgrim2019-03-191-0/+2
* [TargetLowering] Add code size information on isFPImmLegal. NFCAdhemerval Zanella2019-03-181-1/+2
* [ARM] Sink zext/sext operands for add and sub to enable vsubl generation.Florian Hahn2019-03-061-0/+3
* [ARM] Add OptMinSize to ARMSubtargetSam Parker2019-02-081-5/+1
* [SelectionDAG] Codesize: don't expand SHIFT to SHIFT_PARTSSjoerd Meijer2019-01-311-0/+6
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [ARM] Complete the Thumb1 shift+and->shift+shift transforms.Eli Friedman2018-12-201-0/+2
* ARM: use target-specific SUBS node when combining cmp with cmov.Tim Northover2018-12-031-0/+1
* [ARM] Don't expand sdiv when optimising for minsizeSjoerd Meijer2018-11-301-0/+3
* [AtomicExpandPass]: Add a hook for custom cmpxchg expansion in IRAlex Bradbury2018-09-191-1/+2
* ARM: align loops to 4 bytes on Cortex-M3 and Cortex-M4.Tim Northover2018-09-131-0/+2
* [ARM] Enable GEP offset splitting for 32-bit ARM.Eli Friedman2018-08-301-0/+2
* [ARM] Make PerformSHLSimplify add nodes to the DAG worklist correctly.Eli Friedman2018-08-141-0/+3
* [ARM] Adjust AND immediates to make them cheaper to select.Eli Friedman2018-08-101-0/+3
* ARM: don't try to over-align large vectors as arguments.Tim Northover2018-05-031-0/+4
* Remove \brief commands from doxygen comments.Adrian Prantl2018-05-011-3/+3
* [IR][CodeGen] Remove dependency on EVT from IR/Function.cpp. Move EVT to Code...Craig Topper2018-03-291-1/+1
* Fix layering by moving ValueTypes.h from CodeGen to IRDavid Blaikie2018-03-231-1/+1
* Fix layering of MachineValueType.h by moving it from CodeGen to SupportDavid Blaikie2018-03-231-1/+1
* [ARM] Support float literals under XOChristof Douma2018-03-231-0/+1
* [ARM] Armv8.2-A FP16 code generation (part 3/3)Sjoerd Meijer2018-02-061-0/+1
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