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* ARM: support struct byval in llvmManman Ren2012-06-011-15/+262
| | | | | | | | | | We handle struct byval by inserting a pseudo op, which will be expanded to a loop at ExpandISelPseudos. A separate patch for clang will be submitted to enable struct byval. rdar://9877866 llvm-svn: 157793
* Change interface for TargetLowering::LowerCallTo and TargetLowering::LowerCallJustin Holewinski2012-05-251-9/+16
| | | | | | | | | | to pass around a struct instead of a large set of individual values. This cleans up the interface and allows more information to be added to the struct for future targets without requiring changes to each and every target. NV_CONTRIB llvm-svn: 157479
* Use the right register class for LDRrs.Jakob Stoklund Olesen2012-05-201-1/+1
| | | | llvm-svn: 157152
* Add a new target hook "predictableSelectIsExpensive".Benjamin Kramer2012-05-051-0/+3
| | | | | | | | | | | This will be used to determine whether it's profitable to turn a select into a branch when the branch is likely to be predicted. Currently enabled for everything but Atom on X86 and Cortex-A9 devices on ARM. I'm not entirely happy with the name of this flag, suggestions welcome ;) llvm-svn: 156233
* Pacify GCC's -Wreturn-typeMatt Beaumont-Gay2012-05-041-0/+1
| | | | llvm-svn: 156189
* Make ARM and Mips use TargetMachine::getTLSModel()Hans Wennborg2012-05-041-8/+15
| | | | | | | | This moves the logic for selecting a TLS model to a single place, instead of the previous three (ARM, Mips, and X86 which already uses this function). llvm-svn: 156162
* Don't introduce illegal types when creating vmull operations. <rdar://11324364>Bob Wilson2012-04-301-1/+3
| | | | | | | | ARM BUILD_VECTORs created after type legalization cannot use i8 or i16 operands, since those types are not legal. Instead use i32 operands, which will be implicitly truncated by the BUILD_VECTOR to match the element type. llvm-svn: 155824
* Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change ↵Craig Topper2012-04-201-69/+74
| | | | | | since they are equivalent. llvm-svn: 155188
* Handle llvm.fma.* intrinsics. rdar://10914096Evan Cheng2012-04-101-2/+4
| | | | llvm-svn: 154439
* Fix a long standing tail call optimization bug. When a libcall is emittedEvan Cheng2012-04-101-33/+42
| | | | | | | | | | | | | legalizer always use the DAG entry node. This is wrong when the libcall is emitted as a tail call since it effectively folds the return node. If the return node's input chain is not the entry (i.e. call, load, or store) use that as the tail call input chain. PR12419 rdar://9770785 rdar://11195178 llvm-svn: 154370
* When performing a truncating store, it's possible to rearrange the data Chad Rosier2012-04-091-1/+85
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | in-register, such that we can use a single vector store rather then a series of scalar stores. For func_4_8 the generated code vldr d16, LCPI0_0 vmov d17, r0, r1 vadd.i16 d16, d17, d16 vmov.u16 r0, d16[3] strb r0, [r2, #3] vmov.u16 r0, d16[2] strb r0, [r2, #2] vmov.u16 r0, d16[1] strb r0, [r2, #1] vmov.u16 r0, d16[0] strb r0, [r2] bx lr becomes vldr d16, LCPI0_0 vmov d17, r0, r1 vadd.i16 d16, d17, d16 vuzp.8 d16, d17 vst1.32 {d16[0]}, [r2, :32] bx lr I'm not fond of how this combine pessimizes 2012-03-13-DAGCombineBug.ll, but I couldn't think of a way to judiciously apply this combine. This ldrh r0, [r0, #4] strh r0, [r1] becomes vldr d16, [r0] vmov.u16 r0, d16[2] vmov.32 d16[0], r0 vuzp.16 d16, d17 vst1.32 {d16[0]}, [r1, :32] PR11158 rdar://10703339 llvm-svn: 154340
* Update comments and remove unnecessary isVolatile() check.Chad Rosier2012-04-091-3/+5
| | | | llvm-svn: 154336
* Tidy up. 80 columns.Jim Grosbach2012-04-061-1/+2
| | | | llvm-svn: 154226
* There is no portable std::abs overload for int64_t, use the llvm::abs64Chandler Carruth2012-04-061-2/+2
| | | | | | which exists for this purpose. llvm-svn: 154199
* Allow negative immediates in ARM and Thumb2 compares.Jakob Stoklund Olesen2012-04-061-2/+4
| | | | | | | ARM and Thumb2 mode can use cmn instructions to compare against negative immediates. Thumb1 mode can't. llvm-svn: 154183
* Always compute all the bits in ComputeMaskedBits.Rafael Espindola2012-04-041-7/+4
| | | | | | | | This allows us to keep passing reduced masks to SimplifyDemandedBits, but know about all the bits if SimplifyDemandedBits fails. This allows instcombine to simplify cases like the one in the included testcase. llvm-svn: 154011
* ARM target should allow codegenprep to duplicate ret instructions to enable ↵Evan Cheng2012-03-301-1/+1
| | | | | | tailcall opt. rdar://11140249 llvm-svn: 153717
* Try using vmov.i32 to materialize FP32 constants that can't be materialized byLang Hames2012-03-291-23/+54
| | | | | | vmov.f32. llvm-svn: 153696
* Remove unnecessary llvm:: qualificationsCraig Topper2012-03-271-1/+1
| | | | llvm-svn: 153500
* Prune includes and replace uses of ARMRegisterInfo.h with ARMBaeRegisterInfo.hCraig Topper2012-03-261-1/+0
| | | | llvm-svn: 153422
* Replace uses of ARMBaseInstrInfo and ARMTargetMachine with the Base versions.Craig Topper2012-03-251-3/+2
| | | | llvm-svn: 153421
* Perform mul combine when multiplying wiht negative constants.Anton Korobeynikov2012-03-191-18/+48
| | | | | | | Patch by Weiming Zhao! This fixes PR12212 llvm-svn: 153049
* Reorder includes to match coding standards. Fix an issue or two exposed by that.Craig Topper2012-03-171-2/+1
| | | | llvm-svn: 152978
* Use vmov.f32 to materialize f32 consts on ARM. This relaxes constraints onLang Hames2012-03-151-0/+24
| | | | | | | register allocation by allowing all 32 D-registers to be used. Patch by Cameron Zwarich. llvm-svn: 152824
* Convert more static tables of registers used by calling convention to ↵Craig Topper2012-03-111-1/+1
| | | | | | uint16_t to reduce space. llvm-svn: 152538
* Use uint16_t to store registers in callee saved register tables to reduce ↵Craig Topper2012-03-041-1/+1
| | | | | | size of static data. llvm-svn: 151996
* Neuter the optimization I implemented with r107852 and r108258 which turn someEvan Cheng2012-03-011-8/+12
| | | | | | | | | | | | floating point equality comparisons into integer ones with -ffast-math. The issue is the optimization causes +0.0 != -0.0. Now the optimization is only done when one side is known to be 0.0. The other side's sign bit is masked off for the comparison. rdar://10964603 llvm-svn: 151861
* Re-commit r151623 with fix. Only issue special no-return calls if it's a ↵Evan Cheng2012-02-281-5/+14
| | | | | | direct call. llvm-svn: 151645
* Revert r151623 "Some ARM implementaions, e.g. A-series, does return stack ↵Daniel Dunbar2012-02-281-14/+5
| | | | | | prediction. ...", it is breaking the Clang build during the Compiler-RT part. llvm-svn: 151630
* Some ARM implementaions, e.g. A-series, does return stack prediction. That is,Evan Cheng2012-02-281-5/+14
| | | | | | | | | | | | | | | | | the processor keeps a return addresses stack (RAS) which stores the address and the instruction execution state of the instruction after a function-call type branch instruction. Calling a "noreturn" function with normal call instructions (e.g. bl) can corrupt RAS and causes 100% return misprediction so LLVM should use a unconditional branch instead. i.e. mov lr, pc b _foo The "mov lr, pc" is issued in order to get proper backtrace. rdar://8979299 llvm-svn: 151623
* Switch ARM target to register masks.Jakob Stoklund Olesen2012-02-241-0/+6
| | | | | | | | | | | | | I'll let the buildbots determine the compile time improvements from this change, but 464.h264ref has 5% faster codegen at -O2. This patch does cause some assembly changes. Branch folding can make different decisions about calls with dead return values. CriticalAntiDepBreaker may choose different registers because its liveness tracking is affected. MachineCopyPropagation may sometimes leave a dead copy behind. llvm-svn: 151331
* When emitting a cmp with 0 for a lowered select, mask out the highDan Gohman2012-02-241-0/+5
| | | | | | | bits of the value carying the boolean condition, as their contents are undefined. This fixes rdar://10887484. llvm-svn: 151310
* Canonicalize (srl (bswap x), 16) to (rotr (bswap x), 16) if the high 16 bitsEvan Cheng2012-02-231-0/+15
| | | | | | | | of x are zero. This optimizes rev + lsr 16 to rev16. rdar://10750814 llvm-svn: 151230
* Optimize a couple of common patterns involving conditional moves where the falseEvan Cheng2012-02-231-5/+88
| | | | | | | | | | | | | | | | | | | | | value is zero. Instead of a cmov + op, issue an conditional op instead. e.g. cmp r9, r4 mov r4, #0 moveq r4, #1 orr lr, lr, r4 should be: cmp r9, r4 orreq lr, lr, #1 That is, optimize (or x, (cmov 0, y, cond)) to (or.cond x, y). Similarly extend this to xor as well as (and x, (cmov -1, y, cond)) => (and.cond x, y). It's possible to extend this to ADD and SUB but I don't think they are common. rdar://8659097 llvm-svn: 151224
* Make all pointers to TargetRegisterClass const since they are all pointers ↵Craig Topper2012-02-221-7/+7
| | | | | | to static data that should not be modified. llvm-svn: 151134
* Proper support for a bastardized darwin-eabi hybird ABI.Evan Cheng2012-02-211-1/+1
| | | | llvm-svn: 151083
* Improve generated code for extending loads and some trunc stores on ARM.James Molloy2012-02-201-7/+29
| | | | | | Teach TargetSelectionDAG about lengthening loads for vector types and set v4i8 as legal. Allow FP_TO_UINT for v4i16 from v4i32. llvm-svn: 150956
* Don't reserve the R0 and R1 registers here. We don't use these registers, andBill Wendling2012-02-131-4/+9
| | | | | | | marking them as "live-in" into a BB ruins some invariants that the back-end tries to maintain. llvm-svn: 150437
* Make valgrind happy.Jason W Kim2012-02-101-2/+2
| | | | llvm-svn: 150251
* Convert assert(0) to llvm_unreachableCraig Topper2012-02-071-10/+7
| | | | llvm-svn: 149961
* Cleanups for EABI standard functionsAnton Korobeynikov2012-01-291-2/+7
| | | | llvm-svn: 149195
* Use base AAPCS for varargs functions even for AAPCS-VFP CCAnton Korobeynikov2012-01-291-1/+3
| | | | llvm-svn: 149194
* More dead code removal (using -Wunreachable-code)David Blaikie2012-01-201-6/+2
| | | | llvm-svn: 148578
* Refactor variables unused under non-assert builds (& remove two entirely ↵David Blaikie2012-01-161-2/+2
| | | | | | unused variables). llvm-svn: 148230
* Return an ArrayRef from ShuffleVectorSDNode::getMask and push it through ↵Benjamin Kramer2012-01-151-20/+12
| | | | | | CodeGen. llvm-svn: 148218
* Match SelectionDAG logic for enabling movt.Jakob Stoklund Olesen2012-01-071-1/+2
| | | | | | Darwin doesn't do static, and ELF targets only support static. llvm-svn: 147740
* Remove VectorExtras. This unused helper was written for a type of API that ↵Benjamin Kramer2012-01-071-1/+0
| | | | | | is discouraged now. llvm-svn: 147738
* Add variants of the dispatchsetup pseudo for Thumb and !VFP. <rdar://10620138>Bob Wilson2011-12-221-1/+6
| | | | | | | | | | | My change r146949 added register clobbers to the eh_sjlj_dispatchsetup pseudo instruction, but on Thumb1 some of those registers cannot be used. This caused massive failures on the testsuite when compiling for Thumb1. While fixing that, I noticed that the eh_sjlj_setjmp instruction has a "nofp" variant, and I realized that dispatchsetup needs the same thing, so I have added that as well. llvm-svn: 147204
* Make check a bit more strict so we don't call ARM_AM::getFP32Imm with a ↵Eli Friedman2011-12-151-1/+1
| | | | | | value that isn't a 32-bit value. (This is just to be safe; I don't think this actually causes any issues in practice.) llvm-svn: 146700
* Initial CodeGen support for CTTZ/CTLZ where a zero input produces anChandler Carruth2011-12-131-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | undefined result. This adds new ISD nodes for the new semantics, selecting them when the LLVM intrinsic indicates that the undef behavior is desired. The new nodes expand trivially to the old nodes, so targets don't actually need to do anything to support these new nodes besides indicating that they should be expanded. I've done this for all the operand types that I could figure out for all the targets. Owners of various targets, please review and let me know if any of these are incorrect. Note that the expand behavior is *conservatively correct*, and exactly matches LLVM's current behavior with these operations. Ideally this patch will not change behavior in any way. For example the regtest suite finds the exact same instruction sequences coming out of the code generator. That's why there are no new tests here -- all of this is being exercised by the existing test suite. Thanks to Duncan Sands for reviewing the various bits of this patch and helping me get the wrinkles ironed out with expanding for each target. Also thanks to Chris for clarifying through all the discussions that this is indeed the approach he was looking for. That said, there are likely still rough spots. Further review much appreciated. llvm-svn: 146466
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